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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
76 Commits 3 Branches 10 Tags 87 MiB
C 71.5%
Tcl 15.7%
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Stefan Schippers 461e2eae97 add "layer=WIRELAYER" attribute to label texts in LCC schematics so LCC schematic instance looks exactly as schematic. 2020-09-04 10:29:15 +02:00
XSchemWin Joanne fixes: in print_vhdl_primitive, set variable, format, from "vhdl_format" with get_tok_value before checking if its NULL, more work on windows port. 2020-08-10 23:43:20 +02:00
doc added -b/--batch cmd option (__unix__ only) to detach xschem completely from console 2020-08-31 21:24:03 +02:00
scconfig removed unused files 2020-08-24 10:01:41 +02:00
src add "layer=WIRELAYER" attribute to label texts in LCC schematics so LCC schematic instance looks exactly as schematic. 2020-09-04 10:29:15 +02:00
tests Joanne fixes: in print_vhdl_primitive, set variable, format, from "vhdl_format" with get_tok_value before checking if its NULL, more work on windows port. 2020-08-10 23:43:20 +02:00
xschem_library dash attribute for arcs 2020-09-02 23:59:58 +02:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
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Changelog svg and pdf exports use custom layer colors as set in ~/.xschem/colors file if any. 2020-08-30 12:01:48 +02:00
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README populating xschem git repo 2020-08-08 15:47:34 +02:00
README.md Add manual link 2020-08-08 16:04:20 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse. Manual and instructions: http://repo.hu/projects/xschem/xschem_man/xschem_man.html