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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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StefanSchippers 451abb9d5f
added notes for MacOS 'Big Sur' builds. 		2021-09-26 13:24:51 +02:00
XSchemWin update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
doc documentation update about tcleval(...) tcl substitution of attributes by get_tok_value() 2021-09-20 01:57:04 +02:00
scconfig poweramp.sch fixes in sim commands 2021-07-13 18:37:01 +02:00
src interrupting xschem digital simulation with "Simulation->Forced stop tcl scripts" was leaving "tclstop" variable set, causing following simulation to produce erroneousr results. Any new sim resets the flag to 0. 2021-09-25 16:16:30 +02:00
tests update license info 2021-07-27 16:42:54 +02:00
xschem_library interrupting xschem digital simulation with "Simulation->Forced stop tcl scripts" was leaving "tclstop" variable set, causing following simulation to produce erroneousr results. Any new sim resets the flag to 0. 2021-09-25 16:16:30 +02:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
COPYING populating xschem git repo 2020-08-08 15:47:34 +02:00
Changelog bump version to 3.0.0; prepare for 3.0.0 release 2021-09-11 07:53:11 +02:00
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LICENSE update license info 2021-07-27 16:42:54 +02:00
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README update license info 2021-07-27 16:42:54 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in better comments in config.h.in 2020-10-28 00:23:26 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions