A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
Go to file
Stefan Frederik 37f0f7380f added a full adder as an example of a multi-output gate 2020-12-26 19:43:16 +01:00
XSchemWin windows install updates 2020-12-16 10:51:41 +01:00
doc removed obsolete --a3page command option 2020-12-20 20:42:07 +01:00
scconfig -a -m check for unbound instances (Joanne fix) 2020-12-23 15:57:28 +01:00
src added "xschem_simulator" sample example directory for trying logic propagation of probed nets 2020-12-26 19:26:33 +01:00
tests better wire connecting bubble zoom scaling at different snap levels 2020-10-07 19:45:40 +02:00
xschem_library added a full adder as an example of a multi-output gate 2020-12-26 19:43:16 +01:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
AUTHORS populating xschem git repo 2020-08-08 15:47:34 +02:00
COPYING populating xschem git repo 2020-08-08 15:47:34 +02:00
Changelog fix regression due to r1395, updated Changelog, fix set initial window size when doing ps/pdf export from cli 2020-12-17 03:48:34 +01:00
INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
LICENSE Update LICENSE 2020-10-10 11:44:58 +02:00
Makefile populating xschem git repo 2020-08-08 15:47:34 +02:00
Makefile.conf.in populating xschem git repo 2020-08-08 15:47:34 +02:00
README populating xschem git repo 2020-08-08 15:47:34 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md Update README_MacOS.md 2020-12-12 02:18:39 +01:00
config.h.in better comments in config.h.in 2020-10-28 00:23:26 +01:00
configure populating xschem git repo 2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions