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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Frederik 33d9afd3a1 avoid hardcoded (relative) paths for label/pins searching, use more general find_file method 2022-10-17 17:20:40 +02:00
XSchemWin update xschemtest, more robust spice flatten.awk netlist flattener, specifically when translating expressions containing electrical nodes and parameters, all these need to be translated/substituted. 2022-10-12 01:16:23 +02:00
doc Doc updates (sim_pinnumber), example circuits update 2022-10-17 12:45:48 +02:00
scconfig monospaced font in code_shown.sym 2022-08-30 15:54:18 +02:00
src avoid hardcoded (relative) paths for label/pins searching, use more general find_file method 2022-10-17 17:20:40 +02:00
tests Doc updates (sim_pinnumber), example circuits update 2022-10-17 12:45:48 +02:00
xschem_library perf. improvements in plot_raw_custom_data() / ravg_store() 2022-10-17 15:17:47 +02:00
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AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
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README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in remove all xrender and all xcb code, remove detection as well. Fix a couple of potentially uninitialized variables 2022-01-19 00:49:46 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions