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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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stefan schippers 1cf0c820f9 documentation updates 2023-06-05 11:53:51 +02:00
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin fix some errors found by Joanne in test_bus_tap.sch 2023-05-31 00:14:22 +02:00
doc documentation updates 2023-06-05 11:53:51 +02:00
scconfig add "inst_sch_select" example dir in search path in scconfig/hooks.c 2023-05-05 07:59:24 +02:00
src fix missing save_ctx in create_new_tab and create_new_window when creating new tab/window after the 2nd one, leading to wrong context switches. Added trace command on XSCHEM_LIBRARY_PATH when changing search path. `proc set_paths` is automatically called to cache in the new search path. No need to run it manually 2023-06-05 10:54:26 +02:00
tests fix uninitialized wave_color due to regression after rainbow wave color enablement in double dc sweeps; more bus_tap.sym usage in examples; make bus_tap.sym work correctly for all netlist formats 2023-05-27 23:36:10 +02:00
xschem_library add command xschem tab_list, returns window pathname and associated filename loaded 2023-06-03 00:21:55 +02:00
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AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
CMakeLists.txt Added png and embedded graphs to ps and pdf export 2023-01-15 21:34:43 -07:00
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Makefile.conf.in added libjpeg detection code, so postscript image embedding will be disabled if libjpeg not present 2023-01-18 03:33:28 +01:00
README update license info 2021-07-27 16:42:54 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions