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and2_1.sym
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"propagate_to" attribute for pins renamed to "goto"
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2020-12-30 21:26:58 +01:00 |
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and3_1.sym
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"propagate_to" attribute for pins renamed to "goto"
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2020-12-30 21:26:58 +01:00 |
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and4_1.sym
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"propagate_to" attribute for pins renamed to "goto"
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2020-12-30 21:26:58 +01:00 |
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dev-1.sym
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removed redundant update_conn_cues() in some graphic operations; lower priority mux operator for logic sim, Dont change logic value added ("U"), ability to simulate bidirectional switches and simple logic MOS transistor networks. added sample circuits.
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2021-01-12 00:47:56 +01:00 |
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dfrbp_1.sym
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added flip-flop simulation capabilities. added examples: merry xmas greeter and 7 segment display driver and counter.
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2020-12-27 19:20:24 +01:00 |
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dfrtp_1.sym
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new_wire(): update connecting bubbles when inserting new wires and no one is highlighted
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2021-01-19 13:32:45 +01:00 |
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diode_3.sym
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removed redundant update_conn_cues() in some graphic operations; lower priority mux operator for logic sim, Dont change logic value added ("U"), ability to simulate bidirectional switches and simple logic MOS transistor networks. added sample circuits.
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2021-01-12 00:47:56 +01:00 |
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dlrtn_1.sym
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removed redundant update_conn_cues() in some graphic operations; lower priority mux operator for logic sim, Dont change logic value added ("U"), ability to simulate bidirectional switches and simple logic MOS transistor networks. added sample circuits.
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2021-01-12 00:47:56 +01:00 |
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dlrtp_1.sym
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removed redundant update_conn_cues() in some graphic operations; lower priority mux operator for logic sim, Dont change logic value added ("U"), ability to simulate bidirectional switches and simple logic MOS transistor networks. added sample circuits.
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2021-01-12 00:47:56 +01:00 |
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einvp_1.sym
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sample schematic updates
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2021-01-12 03:07:20 +01:00 |
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fa_1.sym
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added rotate operator in logic function description
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2021-01-04 17:24:57 +01:00 |
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giant_label.sym
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num parameter to logic_set() to perform "num" toggling operations
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2020-12-28 20:20:45 +01:00 |
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giant_label2.sym
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remember last directory in export png/svg/pdf/ps, added missing symbols
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2020-12-27 22:59:15 +01:00 |
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inv_2.sym
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"propagate_to" attribute for pins renamed to "goto"
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2020-12-30 21:26:58 +01:00 |
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invert-1.sym
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removed redundant update_conn_cues() in some graphic operations; lower priority mux operator for logic sim, Dont change logic value added ("U"), ability to simulate bidirectional switches and simple logic MOS transistor networks. added sample circuits.
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2021-01-12 00:47:56 +01:00 |
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logic_test.sch
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better handle simulation interruption
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2021-01-12 22:07:27 +01:00 |
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logic_test.sym
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remember last directory in export png/svg/pdf/ps, added missing symbols
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2020-12-27 22:59:15 +01:00 |
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mux2_1.sym
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removed redundant update_conn_cues() in some graphic operations; lower priority mux operator for logic sim, Dont change logic value added ("U"), ability to simulate bidirectional switches and simple logic MOS transistor networks. added sample circuits.
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2021-01-12 00:47:56 +01:00 |
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n.sym
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added missing symbols to xschem_simulator/
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2021-01-12 19:12:40 +01:00 |
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nand2_1.sym
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caching simulation data into "simdata" struct for performance
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2020-12-31 03:08:24 +01:00 |
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nand3_1.sym
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"propagate_to" attribute for pins renamed to "goto"
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2020-12-30 21:26:58 +01:00 |
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nand4_1.sym
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"propagate_to" attribute for pins renamed to "goto"
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2020-12-30 21:26:58 +01:00 |
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nor4_1.sym
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"propagate_to" attribute for pins renamed to "goto"
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2020-12-30 21:26:58 +01:00 |
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o21ai_1.sym
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"propagate_to" attribute for pins renamed to "goto"
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2020-12-30 21:26:58 +01:00 |
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or4_1.sym
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"propagate_to" attribute for pins renamed to "goto"
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2020-12-30 21:26:58 +01:00 |
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p.sym
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added missing symbols to xschem_simulator/
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2021-01-12 19:12:40 +01:00 |
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segment.sym
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example schematics reshaped
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2021-01-04 17:50:16 +01:00 |
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simulate_ff.sch
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better handle simulation interruption
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2021-01-12 22:07:27 +01:00 |
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simulate_ff.sym
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remember last directory in export png/svg/pdf/ps, added missing symbols
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2020-12-27 22:59:15 +01:00 |
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switch-1.sym
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removed redundant update_conn_cues() in some graphic operations; lower priority mux operator for logic sim, Dont change logic value added ("U"), ability to simulate bidirectional switches and simple logic MOS transistor networks. added sample circuits.
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2021-01-12 00:47:56 +01:00 |
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switch_level_sim.sch
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remove unconnected components in switch_level_sim.sch
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2021-01-14 18:53:50 +01:00 |
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xor2_1.sym
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"propagate_to" attribute for pins renamed to "goto"
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2020-12-30 21:26:58 +01:00 |
4fd65005a1