2021-07-27 16:42:54 +02:00
2020-10-28 00:23:26 +01:00
2020-08-08 15:47:34 +02:00
2020-08-08 15:47:34 +02:00
2020-08-08 15:47:34 +02:00
2021-07-27 16:42:54 +02:00
2020-08-08 15:47:34 +02:00
2020-08-08 15:47:34 +02:00
2021-07-27 16:42:54 +02:00
2021-05-03 20:56:10 +00:00
2020-10-08 00:54:06 +02:00

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions

S
Description
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
Readme GPL-2.0
62 MiB
Languages
C 72.7%
Tcl 16.3%
Awk 8.2%
Yacc 0.8%
Scheme 0.5%
Other 1.4%