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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
2,087 Commits 3 Branches 10 Tags 86 MiB
C 71.5%
Tcl 15.8%
Awk 8.2%
Roff 2%
Yacc 0.7%
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stefan schippers 00ef95c90e fix regression: hilight nets not incrementing color (if nets are singlebits) 2023-09-29 10:39:25 +02:00
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin simpler state bits checking in callback() (use rstate to avoid redundant ShiftMask checks) . Enable loading SP Analysis raw files (they are equal as AC analyses) ) 2023-09-28 21:03:28 +02:00
doc added commands xschem get schprop|schvhdprop|schverilogprop|schtedaxprop|schsymbolprop, "xschem create_text" renamed to "xschem text" for syntax consistency 2023-09-29 09:46:31 +02:00
scconfig add "inst_sch_select" example dir in search path in scconfig/hooks.c 2023-05-05 07:59:24 +02:00
src fix regression: hilight nets not incrementing color (if nets are singlebits) 2023-09-29 10:39:25 +02:00
tests more robust netlist_test proc in xschemtest.tcl 2023-08-28 11:44:12 +02:00
xschem_library revert a change in example schematic pcb_test1.sch so xschemtest will not report a false error 2023-09-20 12:35:26 +02:00
.gitignore gitignore update 2023-01-16 13:41:16 -07:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
CMakeLists.txt Added png and embedded graphs to ps and pdf export 2023-01-15 21:34:43 -07:00
Changelog bump to version 3.4.4, updated Changelog 2023-09-14 10:03:14 +02:00
INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
LICENSE update license info 2021-07-27 16:42:54 +02:00
Makefile added install_pdf to create pdf doc from html man pages 2023-07-03 11:38:09 +02:00
Makefile.conf.in added libjpeg detection code, so postscript image embedding will be disabled if libjpeg not present 2023-01-18 03:33:28 +01:00
README update license info 2021-07-27 16:42:54 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in Add description for FIX_BROKEN_TILED_FILL in config.h.in 2023-09-22 01:21:32 +02:00
configure populating xschem git repo 2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions