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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Frederik 008b289e4f ac analysis in graphs (mag + phase, log axis) 2022-02-02 18:33:16 +01:00
XSchemWin fix regression (tcl context was not saved/restored correctly) 2022-02-02 00:11:46 +01:00
doc added new doc files 2022-01-31 17:51:43 +01:00
scconfig remove all xrender and all xcb code, remove detection as well. Fix a couple of potentially uninitialized variables 2022-01-19 00:49:46 +01:00
src ac analysis in graphs (mag + phase, log axis) 2022-02-02 18:33:16 +01:00
tests fix wave panning if a non graph added, better error reporting in png writer function, better flags option names for special objejcts (image and graphs) 2022-01-21 02:18:07 +01:00
xschem_library ac analysis in graphs (mag + phase, log axis) 2022-02-02 18:33:16 +01:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
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Changelog bump version to 3.0.0; prepare for 3.0.0 release 2021-09-11 07:53:11 +02:00
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README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in remove all xrender and all xcb code, remove detection as well. Fix a couple of potentially uninitialized variables 2022-01-19 00:49:46 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions