Stefan Schippers
|
42a8e55956
|
@tcleval() hook in translate()
|
2020-10-12 14:25:12 +02:00 |
|
Stefan Schippers
|
64c0abc58e
|
code refactoring (global context in Xschem_ctx), "New Schematic" or "New Symbol" will set netlist_type to "spice" or "symbol" respectively
|
2020-10-12 13:13:31 +02:00 |
|
Stefan Schippers
|
32f85ac4f4
|
do not force a full hash_wires() on every net insertion; code formatting
|
2020-10-11 13:08:32 +02:00 |
|
Stefan Schippers
|
077fde9350
|
removed redundant command in xschem() command parser
|
2020-10-11 11:26:22 +02:00 |
|
Stefan Schippers
|
b006c82bad
|
slight resize in pin text size for better look. top frame in insert text dialog does not extend vertically.
|
2020-10-11 01:38:28 +02:00 |
|
Stefan Schippers
|
0ce6f6ba5d
|
when netlisting primitive elements (not subcircuits) the "format", "verilog_format", "vhdl_format, "tedax_format" can be specified in instance attributes to override symbol. This allows to adapt primitives (example digital standard cells) to different design kits without using wrapper subcircuits. Together with "symname" redefinition in instance this allows to completely customize element netlisting.
|
2020-10-11 00:13:52 +02:00 |
|
Stefan Schippers
|
617d708009
|
verilog_preprocessor and verilog_timescale now use verilog_format instead of format (which is for spice), corrected verilog_netlist.c; better backslash and quote (") escaping and unescaping when using attribute select combobox; for unquoting use "xschem get_tok tok 2" instead of "xschem get_tok tok 0" + regsub ....(remove backslashes)...
|
2020-10-10 23:21:23 +02:00 |
|
Stefan Schippers
|
31eac64d7a
|
LICENSE cosmetic editing
|
2020-10-10 11:49:12 +02:00 |
StefanSchippers
|
8f7ecbee9f
|
Update LICENSE
|
2020-10-10 11:44:58 +02:00 |
|
Stefan Schippers
|
4d0a3d8f7c
|
allow probing to gaw current in voltage sources in addition to ammeters
|
2020-10-09 22:19:54 +02:00 |
|
Stefan Schippers
|
19753992f4
|
"Option->Show info win" moved to "View->Show ERC info window"
|
2020-10-09 17:36:22 +02:00 |
|
Stefan Schippers
|
644641ed23
|
Preserve existing text (notably license info) in xschem files under version "v" tag; some code refactoring, removed obsoleted comments
|
2020-10-09 17:29:04 +02:00 |
|
Stefan Schippers
|
7649cec683
|
doc updates (developer info)
|
2020-10-09 03:04:49 +02:00 |
|
Stefan Schippers
|
f419381361
|
added support for probing waveforms into gaw if raw file written by Xyce; Xyce uses uppercase, does not wrap voltage nodes into V(...). uses ":" instead of "." as hierarchy separator and other quirks.
|
2020-10-09 01:21:27 +02:00 |
|
Stefan Schippers
|
898a8adfb2
|
some clarifications of steps to be taken to simulate example rom8k circuit
|
2020-10-08 23:24:27 +02:00 |
|
Stefan Schippers
|
f2d7cc4ca8
|
fix hierarchical pathname for current probes to gaw
|
2020-10-08 03:32:23 +02:00 |
|
StefanSchippers
|
bc338881f3
|
Update README.md
|
2020-10-08 00:54:06 +02:00 |
|
Stefan Schippers
|
1f588d843d
|
doing ALt-g on an ammeter (devices->ammeter, a current probe type symbol) will send the current to gaw
|
2020-10-08 00:47:51 +02:00 |
|
Stefan Schippers
|
2287a15e52
|
better wire connecting bubble zoom scaling at different snap levels
|
2020-10-07 19:45:40 +02:00 |
|
Stefan Schippers
|
bbc5a58568
|
added vsqsource, square wave source generator, with only "hi" and "freq" as parameters
|
2020-10-07 18:04:03 +02:00 |
|
Stefan Schippers
|
0f61e0fe0f
|
JL fix regression for path resolution on windows, Esc resets manhattan_lines setting
|
2020-10-07 16:12:33 +02:00 |
|
Stefan Schippers
|
060e53f1d2
|
correctly draw net labels / pins when they are highlighted and user changes their lab attribute so they become unhilighted
|
2020-10-07 03:45:50 +02:00 |
|
Stefan Schippers
|
d9488fa5ea
|
small sample xschemrc fix
|
2020-10-06 21:59:23 +02:00 |
|
Stefan Schippers
|
a10cb2c429
|
added warnings (Options -> Show info window) if components are missing a name=... attribute / if symbols are missing a type=... attribute; eliminated usage of tcl "file normalize..." statements to avoid symlink dereferencing (if using symlinked libraries), aligned version/file_version tags in support awk scripts
|
2020-10-06 16:19:52 +02:00 |
|
Stefan Schippers
|
71f23a5242
|
devices/ symbol fixes
|
2020-10-06 03:20:56 +02:00 |
|
Stefan Schippers
|
11d664b4a8
|
fix a memory leak, spatial hash table tuning, better clear find_inst_to_be_redrawn() nodetable
|
2020-10-05 13:29:57 +02:00 |
|
Stefan Schippers
|
72363cf2d4
|
better wire bbox calculation in find_inst_to_be_redrawn()
|
2020-10-05 04:18:31 +02:00 |
|
Stefan Schippers
|
82051a33e5
|
simplify / break down complex expressions for code readability
|
2020-10-05 03:00:40 +02:00 |
|
Stefan Schippers
|
051b20c014
|
code formating, use some intermediate variables for code readability, line length limited to 124 chars
|
2020-10-04 23:55:43 +02:00 |
|
Stefan Schippers
|
3060217aec
|
simplified complex logical expressions on symbol type by using macros
|
2020-10-04 19:53:09 +02:00 |
|
Stefan Schippers
|
12f74b1265
|
split a couple of xinit.c functions
|
2020-10-04 12:51:34 +02:00 |
|
Stefan Schippers
|
3cf9d53182
|
comments in code
|
2020-10-04 11:19:50 +02:00 |
Christian Svensson
|
ac398820d9
|
make reload dialog text a bit clearer
|
2020-10-04 00:09:57 +02:00 |
|
Stefan SChippers
|
cd556d4d6e
|
fixed typo in read_line() fscanf...
|
2020-10-03 19:50:29 +02:00 |
|
Stefan Schippers
|
34a929f2bf
|
fix rlc.sch sample circuit it was changed for debugging
|
2020-10-03 12:51:31 +02:00 |
|
Stefan Schippers
|
f8708d60c7
|
replace all fscanf(fd, "%*1[\n]"); with fscanf(fd, " "), so CRLF will be handled as well as LF.
|
2020-10-03 12:49:45 +02:00 |
|
Stefan Schippers
|
39cd1a77ed
|
fix a regression in delete(): instance hash was not updated. removed some redundant drawing in copy operations
|
2020-10-03 04:33:52 +02:00 |
|
Stefan Schippers
|
5b72e307df
|
fix erroneous slotted instance recognition (confuse U2[3:0] with U3:2) in translate(), breaking in some cases the "net name on instance pin" feature
|
2020-10-03 01:13:35 +02:00 |
|
Stefan Schippers
|
40d05a2c60
|
fix erroneous slotted instance recognition (confuse U2[3:0] with U3:2) in translate(), breaking in some cases the "net name on instance pin" feature
|
2020-10-03 01:04:57 +02:00 |
|
Stefan Schippers
|
657e8d7fff
|
performance boost in edit attribute on multiple objects when "show net name on symbol pins" is active.
|
2020-10-02 19:09:09 +02:00 |
|
Stefan Schippers
|
164ce52945
|
performance boost of "show net on symbol pins" feature
|
2020-10-02 18:19:31 +02:00 |
|
Stefan Schippers
|
6805335a09
|
regression fix: correctly hash new wires when inserted
|
2020-10-02 16:12:08 +02:00 |
|
Stefan Schippers
|
72f0031611
|
mos_power_ampli.sym and solar_panel.sch examples updated to display symbolnet names on pins
|
2020-10-02 15:45:30 +02:00 |
|
Stefan Schippers
|
621b2157dc
|
more precise bounding box calculation for net highlights (will extend the bbox to cover wide (bus) wires and solder dots) so there are no more "half coloured" connecting dots etc.
|
2020-10-02 03:51:03 +02:00 |
|
Stefan Schippers
|
8807c7250d
|
various graphic rendering fixes for the new "view instance pin net names" function. Fixed some errors in merge schematic in callback.c and paste.c
|
2020-10-02 03:21:22 +02:00 |
|
Stefan Schippers
|
cf0db629c4
|
make move operations display updated @#n:net_name attributes after move operation
|
2020-10-01 02:58:05 +02:00 |
|
Stefan Schippers
|
d706e45987
|
set max width of .c files <=130 chars; Fix netlist regression: if no "lab=value" is given in instance attributes get lab from symbol "template=" string. This was commented out recently and now reverted back. "View->Enable show net names on symbol pins" global menu added: if unset no symbol pin net names will be shown regardless of instance/symbol "net_name=true" and pin @#n:net_name attributes.
|
2020-09-30 23:55:07 +02:00 |
|
Stefan Schippers
|
d0b659c455
|
fix potential uninitialized rot, flip variables for text rotation in load_sym_def()
|
2020-09-30 03:26:45 +02:00 |
|
Stefan Schippers
|
f0b4ab060a
|
optimized translate()
|
2020-09-30 03:06:56 +02:00 |
|
Stefan Schippers
|
3f482fd8a4
|
optimize unselect_all()
|
2020-09-30 02:53:20 +02:00 |