Stefan Frederik
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28cc187b56
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when placing components with lock=true set in template attribute allow to move it to its final position like any other unlocked symbol. Code in place in verilog.awk to do bit unblasting in net-> port associations, but not enalbed it for now as icarus verilog does not handle some bus slices (for example if bus slice direction is different from declared bus direction)
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2022-06-09 09:32:34 +02:00 |
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Stefan Frederik
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ba15e21b24
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preserve ordering in verilog/VHDL signal/wire/reg declarations for consistent netlist hashing/checking
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2021-12-15 15:17:45 +01:00 |
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Stefan Frederik
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00311e7ff1
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update license info
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2021-07-27 16:42:54 +02:00 |
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Stefan Schippers
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35c2d0fa93
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better node multiplicity detection in spice and verilog awk netlist post-processors (\?-?[0-9]+)
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2020-10-16 00:13:39 +02:00 |
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Stefan Schippers
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c87f44a441
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added "xchem load_symbol" command to load a symbol without binding to any instance, text edit attribute "Load" button will start in "$current_dirname"
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2020-10-15 15:37:06 +02:00 |
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Stefan Schippers
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4362c44a8d
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fix various regressions: escape the ? pattern in awk, be more selective in ? node multiplicity tag recognition in spice.awk, yet some more fixes in abs_sym_path thanks to JL
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2020-10-15 13:38:27 +02:00 |
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Stefan Schippers
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e82f270f61
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replaced @ character with ? for spice netlist node multiplicity tags, so translate() will not try to expand them, do not print erc warnings for "non electrical" symbols (architecture, package, port_attributes, use, etc), print_spice_element() result string will be forwarded to translate() if enclosed within tcleval(...), so all @vars will be expanded. translate() in turn will forward to tcl_hook() if necessary.
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2020-10-14 23:15:05 +02:00 |
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Stefan SChippers
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5e8df730a0
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |