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@ -88,6 +88,12 @@ p{padding: 15px 30px 10px;}
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circuit. The assumption for all alternate circuits created using the methods explained above is that the
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alternate circuits have all the same interface as the base circuit (same input, output, inout pins, in the same order).
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</p><br><br>
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<p class="important">
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Note: all the above concepts are valid for VHDL, Verilog and tEDAx netlists by replacing the
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<kbd>spice_sym_def</kbd> attribute with <kbd>vhdl_sym_def</kbd>, <kbd>verilog_sym_def</kbd> and <kbd>tedax_sym_def</kbd>
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respectively.
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</p><br><br>
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<!-- end of slide -->
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<div class="filler"></div>
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</div>
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