doc updates

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stefan schippers 2023-04-13 22:33:56 +02:00
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@ -88,6 +88,12 @@ p{padding: 15px 30px 10px;}
circuit. The assumption for all alternate circuits created using the methods explained above is that the
alternate circuits have all the same interface as the base circuit (same input, output, inout pins, in the same order).
</p><br><br>
<p class="important">
Note: all the above concepts are valid for VHDL, Verilog and tEDAx netlists by replacing the
<kbd>spice_sym_def</kbd> attribute with <kbd>vhdl_sym_def</kbd>, <kbd>verilog_sym_def</kbd> and <kbd>tedax_sym_def</kbd>
respectively.
</p><br><br>
<!-- end of slide -->
<div class="filler"></div>
</div>