diff --git a/src/actions.c b/src/actions.c
index 8d6ef969..1c9866e9 100644
--- a/src/actions.c
+++ b/src/actions.c
@@ -1062,6 +1062,7 @@ void descend_schematic(int instnumber)
      * -1 : user cancel
      *  0 : file not saved due to errors or per user request
      */
+    dbg(0, "ret=%d\n", ret);
     if(ret == 0) clear_all_hilights();
     if(ret == -1) return; /* user cancel */
   }
diff --git a/src/save.c b/src/save.c
index 18fa4ca7..d76031cc 100644
--- a/src/save.c
+++ b/src/save.c
@@ -2341,8 +2341,21 @@ void descend_symbol(void)
   rebuild_selected_array();
   if(xctx->lastsel > 1)  return;
   if(xctx->lastsel==1 && xctx->sel_array[0].type==ELEMENT) {
-    if(xctx->modified) {
-      if(save(1)) return;
+    if(xctx->modified)
+    {
+      int ret;
+  
+      ret = save(1);
+      /* if circuit is changed but not saved before descending
+       * state will be inconsistent when returning, can not propagare hilights
+       * save() return value:
+       *  1 : file saved 
+       * -1 : user cancel
+       *  0 : file not saved due to errors or per user request
+       */
+      dbg(0, "ret=%d\n", ret);
+      if(ret == 0) clear_all_hilights();
+      if(ret == -1) return; /* user cancel */
     }
     my_snprintf(name, S(name), "%s", xctx->inst[xctx->sel_array[0].n].name);
     /* dont allow descend in the default missing symbol */
diff --git a/xschem_library/logic/test_mos_verilog.sch b/xschem_library/logic/test_mos_verilog.sch
index fbc98cc8..e25971f3 100644
--- a/xschem_library/logic/test_mos_verilog.sch
+++ b/xschem_library/logic/test_mos_verilog.sch
@@ -66,3 +66,4 @@ C {lab_pin.sym} 550 -230 0 0 {name=l11 sig_type=std_logic lab=IN verilog_type=re
 C {lab_pin.sym} 720 -310 0 1 {name=l12 sig_type=std_logic lab=OUT2}
 C {pmos4.sym} 630 -390 0 0 {name=M4 model=pmos w=5u l=0.18u m=1}
 C {vdd.sym} 710 -390 0 0 {name=l13 lab=VDD value=1}
+C {noconn.sym} 300 -230 1 0 {name=l14}