From 95095e97d00af7f7d59a8de6f5da13e66f00ccb1 Mon Sep 17 00:00:00 2001
From: Stefan Frederik <stefan.schippers@gmail.com>
Date: Sun, 21 Nov 2021 01:45:16 +0100
Subject: [PATCH] add delays in logic/test_mos_verilog.sch

---
 xschem_library/logic/test_mos_verilog.sch | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/xschem_library/logic/test_mos_verilog.sch b/xschem_library/logic/test_mos_verilog.sch
index 968eaf15..8ff801a6 100644
--- a/xschem_library/logic/test_mos_verilog.sch
+++ b/xschem_library/logic/test_mos_verilog.sch
@@ -21,8 +21,8 @@ N 390 -220 450 -220 { lab=IN}
 N 490 -300 610 -300 { lab=OUT}
 N 450 -380 450 -340 { lab=OUT}
 N 450 -340 490 -340 { lab=OUT}
-C {nmos4.sym} 470 -220 0 0 {name=M1 model=nmos w=5u l=0.18u m=1}
-C {nmos4_depl.sym} 470 -380 0 0 {name=M3 model=nmos w=5u l=0.18u m=1}
+C {nmos4.sym} 470 -220 0 0 {name=M1 model=nmos w=5u l=0.18u m=1 del=10}
+C {nmos4_depl.sym} 470 -380 0 0 {name=M3 model=nmos w=5u l=0.18u m=1 del=10}
 C {gnd.sym} 550 -380 0 0 {name=l1 lab=GND}
 C {gnd.sym} 550 -220 0 0 {name=l2 lab=GND}
 C {gnd.sym} 490 -150 0 0 {name=l3 lab=GND value=0}