From 6be0fc392b2de359a7f0700aa661aff312e035c6 Mon Sep 17 00:00:00 2001 From: Stefan Frederik Date: Fri, 7 Oct 2022 23:29:42 +0200 Subject: [PATCH] refactoring of netlister code --- XSchemWin/XSchemWix/xschemrc | 74 +- src/callback.c | 23 +- src/check.c | 13 +- src/get_malloc_id.awk | 12 +- src/netlist.c | 1105 +++++++++++--------- src/node_hash.c | 8 +- src/select.c | 23 +- src/xschem.h | 1 + xschem_library/examples/doublepin.sch | 2 +- xschem_library/examples/doublepin.sym | 22 +- xschem_library/examples/test_doublepin.sch | 219 ++-- xschem_library/ngspice/inv_ngspice.sym | 5 +- 12 files changed, 839 insertions(+), 668 deletions(-) diff --git a/XSchemWin/XSchemWix/xschemrc b/XSchemWin/XSchemWix/xschemrc index f4775d3e..8881030b 100644 --- a/XSchemWin/XSchemWix/xschemrc +++ b/XSchemWin/XSchemWix/xschemrc @@ -15,28 +15,27 @@ #### XSCHEM SYSTEM-WIDE DESIGN LIBRARY PATHS: XSCHEM_LIBRARY_PATH ########################################################################### #### If unset xschem starts with XSCHEM_LIBRARY_PATH set to the default, typically: -# /home/schippes/.xschem/xschem_library -# /home/schippes/share/xschem/xschem_library/devices -# /home/schippes/share/doc/xschem/examples -# /home/schippes/share/doc/xschem/ngspice -# /home/schippes/share/doc/xschem/logic -# /home/schippes/share/doc/xschem/xschem_simulator -# /home/schippes/share/doc/xschem/binto7seg -# /home/schippes/share/doc/xschem/pcb -# /home/schippes/share/doc/xschem/rom8k +#### /home/schippes/.xschem/xschem_library +#### /home/schippes/share/xschem/xschem_library/devices +#### /home/schippes/share/doc/xschem/examples +#### /home/schippes/share/doc/xschem/ngspice +#### /home/schippes/share/doc/xschem/logic +#### /home/schippes/share/doc/xschem/xschem_simulator +#### /home/schippes/share/doc/xschem/binto7seg +#### /home/schippes/share/doc/xschem/pcb +#### /home/schippes/share/doc/xschem/rom8k #### For testing in build src directory #### if unset following paths are set and maintained if existing: -# -# ~/.xschem/xschem_library -# ../xschem_library/devices -# ../xschem_library/examples -# ../xschem_library/ngspice -# ../xschem_library/logic -# ../xschem_library/xschem_simulator -# ../xschem_library/binto7seg -# ../xschem_library/pcb -# ../xschem_library/rom8k +#### ~/.xschem/xschem_library +#### ../xschem_library/devices +#### ../xschem_library/examples +#### ../xschem_library/ngspice +#### ../xschem_library/logic +#### ../xschem_library/xschem_simulator +#### ../xschem_library/binto7seg +#### ../xschem_library/pcb +#### ../xschem_library/rom8k #### For testing after installation: uncomment following lines # set xschem_doc_dir [file dirname ${XSCHEM_SHAREDIR}]/doc/xschem @@ -185,6 +184,11 @@ #### editing a new component if clicking on a new component. #### default: enabled (1) # set autofocus_mainwindow 0 + +#### set component browser always above drawing canvas. +#### default: enabled (1) +# set component_browser_on_top 0 + ########################################################################### #### EXPORT FORMAT TRANSLATORS, PNG AND PDF ########################################################################### @@ -342,40 +346,40 @@ set editor {notepad.exe} ########################################################################### #### TABBED WINDOWS ########################################################################### -# default: not enabled. Interface can be changed runtime if only one window -# or tab is open. +#### default: not enabled. Interface can be changed runtime if only one window +#### or tab is open. # set tabbed_interface 1 ########################################################################### #### CASE INSENSITIVE SYMBOL LOOKUP ########################################################################### -## this option might be useful on filesystems that are case insensitive and -## on designs ported from windows where case of file names does not matter. -## if this option is set symbol lookup will be case insensitive, -## so a symbol reference 'AMPLI.SYM' will match with 'ampli.sym' or -## Amply.sym on disk. File system must be case insensitive for this to work, -## like FAT32 or NTFS. -## Do not set this option if you don't know what you are doing. -## Default: not enabled (0) +#### this option might be useful on filesystems that are case insensitive and +#### on designs ported from windows where case of file names does not matter. +#### if this option is set symbol lookup will be case insensitive, +#### so a symbol reference 'AMPLI.SYM' will match with 'ampli.sym' or +#### Amply.sym on disk. File system must be case insensitive for this to work, +#### like FAT32 or NTFS. +#### Do not set this option if you don't know what you are doing. +#### Default: not enabled (0) # set case_insensitive 1 ########################################################################### #### SHOW HIDDEN TEXTS ########################################################################### -## This option shows text objects even if they have attribute 'hide=true' set -## default: 0 (not set) +#### This option shows text objects even if they have attribute 'hide=true' set +#### default: 0 (not set) # set show_hidden_texts 1 ########################################################################### #### HIDE GRAPHS IF NO SPICE DATA LOADED ########################################################################### -## if enabled graphs will be hidden if no data is loaded. -## default: not enabled (0) +#### if enabled graphs will be hidden if no data is loaded. +#### default: not enabled (0) # set hide_empty_graphs 0 ########################################################################### #### LIVE BACKANNOTATION OF DATA AT CURSOR 2 (B) POSITION ########################################################################### -## if enabled will backannotate values in schematic at cursor 'b' position -## in graph. Default: not enabled (0) +#### if enabled will backannotate values in schematic at cursor 'b' position +#### in graph. Default: not enabled (0) # set live_cursor2_backannotate 1 \ No newline at end of file diff --git a/src/callback.c b/src/callback.c index 69bbd54b..d26ff796 100644 --- a/src/callback.c +++ b/src/callback.c @@ -1131,9 +1131,12 @@ int callback(const char *winpath, int event, int mx, int my, KeySym key, xctx->mousey=Y_TO_XSCHEM(my); xctx->mousex_snap=my_round(xctx->mousex / c_snap) * c_snap; xctx->mousey_snap=my_round(xctx->mousey / c_snap) * c_snap; - my_snprintf(str, S(str), "mouse = %.16g %.16g - selected: %d path: %s", - xctx->mousex_snap, xctx->mousey_snap, xctx->lastsel, xctx->sch_path[xctx->currsch] ); - statusmsg(str,1); + + if(abs(mx-xctx->mx_save) > 8 || abs(my-xctx->my_save) > 8 ) { + my_snprintf(str, S(str), "mouse = %.16g %.16g - selected: %d path: %s", + xctx->mousex_snap, xctx->mousey_snap, xctx->lastsel, xctx->sch_path[xctx->currsch] ); + statusmsg(str,1); + } switch(event) { @@ -1201,12 +1204,14 @@ int callback(const char *winpath, int event, int mx, int my, KeySym key, #endif if(xctx->semaphore >= 2) break; if(xctx->ui_state) { - my_snprintf(str, S(str), "mouse = %.16g %.16g - selected: %d w=%.16g h=%.16g", - xctx->mousex_snap, xctx->mousey_snap, - xctx->lastsel , - xctx->mousex_snap-xctx->mx_double_save, xctx->mousey_snap-xctx->my_double_save - ); - statusmsg(str,1); + if(abs(mx-xctx->mx_save) > 8 || abs(my-xctx->my_save) > 8 ) { + my_snprintf(str, S(str), "mouse = %.16g %.16g - selected: %d w=%.16g h=%.16g", + xctx->mousex_snap, xctx->mousey_snap, + xctx->lastsel , + xctx->mousex_snap-xctx->mx_double_save, xctx->mousey_snap-xctx->my_double_save + ); + statusmsg(str,1); + } } if(xctx->ui_state & STARTZOOM) zoom_rectangle(RUBBER); if(xctx->ui_state & STARTSELECT && !(xctx->ui_state & (PLACE_SYMBOL | STARTPAN | PLACE_TEXT)) ) { diff --git a/src/check.c b/src/check.c index 684ff1c1..49e29377 100644 --- a/src/check.c +++ b/src/check.c @@ -381,10 +381,8 @@ void trim_wires(void) void break_wires_at_pins(void) { int k, i, j, r, rects, sqx, sqy; - short rot, flip; Wireentry *wptr; - xRect *rct; - double x0, y0, rx1, ry1; + double x0, y0; int changed=0; hash_wires(); @@ -398,14 +396,7 @@ void break_wires_at_pins(void) { for(r=0;rinst[k].ptr+ xctx->sym)->rect[PINLAYER]; - x0=(rct[r].x1+rct[r].x2)/2; - y0=(rct[r].y1+rct[r].y2)/2; - rot=xctx->inst[k].rot; - flip=xctx->inst[k].flip; - ROTATION(rot, flip, 0.0,0.0,x0,y0,rx1,ry1); - x0=xctx->inst[k].x0+rx1; - y0=xctx->inst[k].y0+ry1; + get_inst_pin_coord(k, r, &x0, &y0); get_square(x0, y0, &sqx, &sqy); for(wptr=xctx->wire_spatial_table[sqx][sqy]; wptr; wptr=wptr->next) { i = wptr->n; diff --git a/src/get_malloc_id.awk b/src/get_malloc_id.awk index 87cb016f..27d4bc3b 100755 --- a/src/get_malloc_id.awk +++ b/src/get_malloc_id.awk @@ -51,8 +51,14 @@ vhdl_netlist.c \ xinit.c \ | sort -n \ | awk '{ - if(n>0 && $1 <= prev) print ">>>>>>>>>>> ERROR >>>>>>>>>" - else if(n++>0 && $1 != prev+1) print ">>>>>>>>>>>>>>>>>>>>>>>>>>>" + if(n>0 && $1 <= prev) print ">>>>>>>>>>> ERROR >>>>>>>>> " $0 + else if(n++>0 && $1 != prev+1) { + if($1-1 > prev+1) + print ">>>>>>>>>>> FREE >>>>>>>>> " prev+1 ":" $1-1 + else + print ">>>>>>>>>>> FREE >>>>>>>>> " $1-1 + + print + } else print prev = $1 - print }' diff --git a/src/netlist.c b/src/netlist.c index dbb36cb8..3e201b4d 100644 --- a/src/netlist.c +++ b/src/netlist.c @@ -461,66 +461,46 @@ static void signal_short( char *n1, char *n2) static void wirecheck(int k) /* recursive routine */ { - int tmpi,tmpj, counti,countj,i,j; - int touches; - double x1, y1, x2, y2; - int x1a, x2a, y1a, y2a; - Wireentry *ptr2; - xWire * const wire = xctx->wire; + int tmpi, tmpj, counti, countj, i, j, touches, x1a, x2a, y1a, y2a; + double x1, y1, x2, y2; + Wireentry *ptr2; + xWire * const wire = xctx->wire; - x1=wire[k].x1; - x2=wire[k].x2; - y1=wire[k].y1; - y2=wire[k].y2; - + x1 = wire[k].x1; y1 = wire[k].y1; + x2 = wire[k].x2; y2 = wire[k].y2; /* ordered bbox */ RECTORDER(x1, y1, x2, y2); /* calculate square 4 1st bbox point of wire[k] */ - x1a=(int)floor(x1/BOXSIZE) ; - y1a=(int)floor(y1/BOXSIZE) ; - + x1a = (int)floor(x1 / BOXSIZE); + y1a = (int)floor(y1 / BOXSIZE); /* calculate square 4 2nd bbox point of wire[k] */ - x2a=(int)floor(x2/BOXSIZE); - y2a=(int)floor(y2/BOXSIZE); - + x2a = (int)floor(x2 / BOXSIZE); + y2a = (int)floor(y2 / BOXSIZE); /*loop thru all squares that intersect bbox of wire[k] */ - counti=0; - for(i=x1a; i<=x2a && counti < NBOXES; i++) - { - counti++; - tmpi=i%NBOXES; if(tmpi<0) tmpi+=NBOXES; - countj=0; - for(j=y1a; j<=y2a && countj < NBOXES; j++) - { - countj++; - tmpj=j%NBOXES; if(tmpj<0) tmpj+=NBOXES; - /*check if wire[k] touches wires in square [tmpi, tmpj] */ - ptr2=xctx->wire_spatial_table[tmpi][tmpj]; - while(ptr2) - { - if(wire[ptr2->n].node) {ptr2=ptr2->next; continue;} /* 20171207 net already checked. Move on */ - if(ptr2->n != k) { /* 20171204 avoid checking wire against itself */ - touches = touch(wire[k].x1,wire[k].y1,wire[k].x2,wire[k].y2, - wire[ptr2->n].x1,wire[ptr2->n].y1) || - touch(wire[k].x1,wire[k].y1,wire[k].x2,wire[k].y2, - wire[ptr2->n].x2,wire[ptr2->n].y2) || - touch(wire[ptr2->n].x1,wire[ptr2->n].y1,wire[ptr2->n].x2, - wire[ptr2->n].y2, wire[k].x1,wire[k].y1) || - touch(wire[ptr2->n].x1,wire[ptr2->n].y1,wire[ptr2->n].x2, - wire[ptr2->n].y2, wire[k].x2,wire[k].y2); - if( touches ) - { - my_strdup(239, &wire[ptr2->n].node, wire[k].node); - my_strdup(240, &wire[ptr2->n].prop_ptr, - subst_token(wire[ptr2->n].prop_ptr, "lab", wire[ptr2->n].node)); - wirecheck(ptr2->n); /* recursive check */ - } - } - ptr2=ptr2->next; + counti = 0; + for(i = x1a; i <= x2a && counti < NBOXES; i++) { + counti++; + tmpi = i % NBOXES; if(tmpi < 0) tmpi += NBOXES; + countj = 0; + for(j = y1a; j <= y2a && countj < NBOXES; j++) { + countj++; + tmpj = j % NBOXES; if(tmpj < 0) tmpj += NBOXES; + /*check if wire[k] touches wires in square [tmpi, tmpj] */ + for(ptr2 = xctx->wire_spatial_table[tmpi][tmpj]; ptr2; ptr2 = ptr2->next) { + if(ptr2->n == k || wire[ptr2->n].node) {continue;} /* itself or net already checked. Move on */ + touches = + touch(wire[k].x1,wire[k].y1,wire[k].x2,wire[k].y2, wire[ptr2->n].x1,wire[ptr2->n].y1) || + touch(wire[k].x1,wire[k].y1,wire[k].x2,wire[k].y2, wire[ptr2->n].x2,wire[ptr2->n].y2) || + touch(wire[ptr2->n].x1,wire[ptr2->n].y1,wire[ptr2->n].x2, wire[ptr2->n].y2, wire[k].x1,wire[k].y1) || + touch(wire[ptr2->n].x1,wire[ptr2->n].y1,wire[ptr2->n].x2, wire[ptr2->n].y2, wire[k].x2,wire[k].y2); + if( touches ) { + my_strdup(239, &wire[ptr2->n].node, wire[k].node); + my_strdup(240, &wire[ptr2->n].prop_ptr, + subst_token(wire[ptr2->n].prop_ptr, "lab", wire[ptr2->n].node)); + wirecheck(ptr2->n); /* recursive check */ + } + } } - dbg(2, "wirecheck(): %d/%d\n", tmpi,tmpj ); - } - dbg(2, "wirecheck(): \n"); } } @@ -541,6 +521,17 @@ void set_tcl_netlist_type(void) } } +static void set_unnamed_net(int i) +{ + char tmp_str[30]; + my_snprintf(tmp_str, S(tmp_str), "#net%d", get_unnamed_node(1,0,0)); + my_strdup(265, &xctx->wire[i].node, tmp_str); + my_strdup(266, &xctx->wire[i].prop_ptr, subst_token(xctx->wire[i].prop_ptr, "lab", tmp_str)); + /* insert unnamed wire name in hash table */ + bus_node_hash_lookup(tmp_str, "", XINSERT, 0,"","","",""); + wirecheck(i); +} + /* what==0 -> initialize */ /* what==1 -> get new node name, net## */ /* what==2 -> update multiplicity */ @@ -550,17 +541,23 @@ int get_unnamed_node(int what, int mult,int node) int i; dbg(2, "get_unnamed_node(): what=%d mult=%d node=%d\n", what, mult, node); - if (what==0) /* initialize unnamed node data structures */ + if(what==0) /* initialize unnamed node data structures */ { xctx->new_node=0; my_free(828, &xctx->node_mult); xctx->node_mult_size=0; return 0; } - else if (what==1) /* get a new unique unnamed node */ + else if(what==1) /* get a new unique unnamed node */ { - ++xctx->new_node; - if (xctx->new_node>= xctx->node_mult_size) /* enlarge array and zero it */ + char tmp_str[30]; + do { + ++xctx->new_node; + my_snprintf(tmp_str, S(tmp_str), "net%d", xctx->new_node); + /* JL avoid autonamed nets clash with user defined 'net#' names */ + } while (bus_node_hash_lookup(tmp_str, "", XLOOKUP, 0, "", "", "", "")!=NULL); + + while(xctx->new_node>= xctx->node_mult_size) /* enlarge array and zero it */ { xctx->node_mult_size += CADCHUNKALLOC; my_realloc(242, &xctx->node_mult, sizeof(int) * xctx->node_mult_size ); @@ -571,8 +568,8 @@ int get_unnamed_node(int what, int mult,int node) } else if(what==2) /* update node multiplicity if given mult is lower */ { - if (xctx->node_mult[node]==0) xctx->node_mult[node]=mult; - else if (multnode_mult[node]) xctx->node_mult[node]=mult; + if(xctx->node_mult[node]==0) xctx->node_mult[node]=mult; + else if(mult < xctx->node_mult[node]) xctx->node_mult[node]=mult; return 0; } else /* what=3 , return node multiplicity */ @@ -622,6 +619,376 @@ int record_global_node(int what, FILE *fp, char *node) return 0; } +void get_inst_pin_coord(int i, int j, double *x, double *y) +{ + xRect *rct; + int rects, rot, flip; + double x0, y0, rx1, ry1; + xInstance * const inst = xctx->inst; + rects = (inst[i].ptr+ xctx->sym)->rects[PINLAYER]; + if(j < rects) { + rct=(inst[i].ptr+ xctx->sym)->rect[PINLAYER]; + x0=(rct[j].x1+rct[j].x2)/2; + y0=(rct[j].y1+rct[j].y2)/2; + rot=inst[i].rot; + flip=inst[i].flip; + ROTATION(rot, flip, 0.0,0.0,x0,y0,rx1,ry1); + *x=inst[i].x0+rx1; + *y=inst[i].y0+ry1; + } else { + *x = 0; + *y = 0; + } +} + +static void set_inst_node(int i, int j, const char *node, int for_netlist) +{ + xInstance * const inst = xctx->inst; + my_strdup(275, &inst[i].node[j], node); + if(!for_netlist) { + bus_node_hash_lookup(inst[i].node[j],"", XINSERT, 0,"","","",""); + } else { + bus_node_hash_lookup(inst[i].node[j], + get_tok_value( (inst[i].ptr+ xctx->sym)->rect[PINLAYER][j].prop_ptr, "dir",0), + XINSERT, 0,"","","",""); + } +} + +static void name_non_label_inst_pins(for_netlist) +{ + char tmp_str[30]; /* overflow safe */ + double x0, y0; + int sqx, sqy; + int touches=0; + int touches_unnamed=0; + Wireentry *wptr; + Instpinentry *iptr; + int i,j, rects; + char *type=NULL; + int inst_mult, pin_mult; + xInstance * const inst = xctx->inst; + int const instances = xctx->instances; + + /* name instance pins of non (label,pin) instances */ + dbg(2, "prepare_netlist_structs(): assigning node names on instance pins\n"); + for (i=0;isym)->type); + if(type && !IS_LABEL_OR_PIN(type) ) { + rects = (inst[i].ptr+ xctx->sym)->rects[PINLAYER]; + expandlabel(inst[i].instname, &inst_mult); + for (j=0;jwire_spatial_table[sqx][sqy]; wptr; wptr = wptr->next) { + if(touch(xctx->wire[wptr->n].x1, xctx->wire[wptr->n].y1, + xctx->wire[wptr->n].x2, xctx->wire[wptr->n].y2, x0,y0)) { + /* short circuit check */ + if(touches) { + if(for_netlist>0) signal_short(inst[i].node[j], xctx->wire[wptr->n].node); + } + if(!touches) { + set_inst_node(i, j, xctx->wire[wptr->n].node, for_netlist); + if(xctx->wire[wptr->n].node[0]=='#') { /* unnamed node, update its multiplicity */ + expandlabel(get_tok_value( + (inst[i].ptr+ xctx->sym)->rect[PINLAYER][j].prop_ptr,"name",0),&pin_mult); + get_unnamed_node(2, pin_mult * inst_mult, atoi((inst[i].node[j])+4) ); + } + } /* end if(!touches) */ + touches=1; + } + } + dbg(2, "prepare_netlist_structs(): from other instances\n"); + touches_unnamed=0; + for(iptr=xctx->instpin_spatial_table[sqx][sqy]; iptr; iptr= iptr->next) { + if(iptr->n == i || inst[iptr->n].ptr < 0) continue; + if((iptr->x0==x0) && (iptr->y0==y0)) { + if(inst[iptr->n].node && inst[iptr->n].node[iptr->pin] != NULL) { + /* short circuit check */ + if(touches) { + if(for_netlist>0) signal_short(inst[i].node[j], inst[iptr->n].node[iptr->pin]); + } + if(!touches) { + set_inst_node(i, j, inst[iptr->n].node[iptr->pin], for_netlist); + if((inst[i].node[j])[0] == '#') { + expandlabel(get_tok_value( + (inst[i].ptr+ xctx->sym)->rect[PINLAYER][j].prop_ptr,"name",0),&pin_mult ); + get_unnamed_node(2, pin_mult * inst_mult, atoi((inst[i].node[j])+4)); + } + } + touches=1; + } /* end if(inst[iptr->n].node[iptr->pin] != NULL) */ + else { /* touches instance with unnamed pins */ + touches_unnamed=1; + } + } /* end if( (iptr->x0==x0) && (iptr->y0==y0) ) */ + } + /* pin did not touch named pins or nets so we name it now */ + dbg(2, "prepare_netlist_structs(): naming the other pins\n"); + if(!touches) { /* pin does not touch any other instance pin with non NULL node[] field ...*/ + if(touches_unnamed) { /* ... but touches some other instance pin, so create unnamed net */ + expandlabel(get_tok_value( + (inst[i].ptr+ xctx->sym)->rect[PINLAYER][j].prop_ptr,"name",0), &pin_mult); + /* done at beginning of for(i) loop 20171210 */ + /* expandlabel(get_tok_value( */ + /* inst[i].prop_ptr,"name",0), &inst_mult); */ + my_snprintf( tmp_str, S(tmp_str), "#net%d", get_unnamed_node(1, pin_mult * inst_mult, 0)); + set_inst_node(i, j, tmp_str, for_netlist); + } + } + } /* for(j=0;jinst; + int const instances = xctx->instances; + + /* name generic pins from attached labels */ + dbg(2, "prepare_netlist_structs(): naming generics from attached labels\n"); + if(for_netlist) for (i=0;isym)->type); + if(type && !IS_LABEL_OR_PIN(type) ) { + if((generic_rects = (inst[i].ptr+ xctx->sym)->rects[GENERICLAYER]) > 0) { + rects = (inst[i].ptr+ xctx->sym)->rects[PINLAYER]; + for (j=rects;jsym)->rect[GENERICLAYER]; + x0=(rct[j-rects].x1+rct[j-rects].x2)/2; + y0=(rct[j-rects].y1+rct[j-rects].y2)/2; + rot=inst[i].rot; + flip=inst[i].flip; + ROTATION(rot, flip, 0.0,0.0,x0,y0,rx1,ry1); + x0=inst[i].x0+rx1; + y0=inst[i].y0+ry1; + get_square(x0, y0, &sqx, &sqy); + + for(iptr=xctx->instpin_spatial_table[sqx][sqy]; iptr; iptr = iptr ->next) { + if(iptr->n == i) continue; + if((iptr->x0==x0) && (iptr->y0==y0)) { + if((inst[iptr->n].ptr+ xctx->sym)->type && inst[iptr->n].node[iptr->pin] != NULL && + !strcmp((inst[iptr->n].ptr+ xctx->sym)->type, "label")) { + dbg(2, "prepare_netlist_structs(): naming generic %s\n", + inst[iptr->n].node[iptr->pin]); + my_strdup(268, &inst[i].node[j], get_tok_value(inst[iptr->n].prop_ptr,"value",0) ); + if(!for_netlist) { + my_strdup(270, &sig_type,""); + bus_node_hash_lookup(inst[iptr->n].node[iptr->pin],"", + XINSERT, 1, sig_type,"", "",""); + } else { + my_strdup(271, &sig_type,get_tok_value( + (inst[i].ptr+ xctx->sym)->rect[GENERICLAYER][j-rects].prop_ptr, "sig_type",0)); + /* insert generic label in hash table as a port so it will not */ + /* be declared as a signal in the vhdl netlist. this is a workaround */ + /* that should be fixed 25092001 */ + bus_node_hash_lookup(inst[iptr->n].node[iptr->pin], + get_tok_value((inst[i].ptr+ xctx->sym)->rect[GENERICLAYER][j-rects].prop_ptr, "dir",0), + XINSERT, 1, sig_type,"", "",""); + } + } /* end if(inst[iptr->n].node[iptr->pin] != NULL) */ + } /* end if( (iptr->x0==x0) && (iptr->y0==y0) ) */ + } /* end for(iptr=xctx->instpin_spatial_table[sqx][sqy]; iptr; iptr = iptr ->next) */ + } /* end for(j=0;j0) */ + } /* end if(type not a label nor pin)... */ + } /* end for(i...) */ +} + +static void name_nodes_of_pins_labels_and_attached_nets(for_netlist) +{ + double x0, y0; + int i, sqx, sqy; + int port; + Wireentry *wptr; + char *dir=NULL; + char *type=NULL; + char *sig_type=NULL; + char *verilog_type=NULL; + char *value=NULL; + char *class=NULL; + char *global_node=NULL; + int print_erc; + xInstance * const inst = xctx->inst; + int const instances = xctx->instances; + static int startlevel = 0; /* safe to keep even with multiple schematic windows, netlist is not interruptable */ + + if(xctx->netlist_count == 0 ) startlevel = xctx->currsch; + dbg(2, "prepare_netlist_structs(): naming pins from attrs\n"); + /* print_erc is 1 the first time prepare_netlist_structs() is called on top level while + * doing the netlist, when netlist of sub blocks is completed and toplevel is reloaded + * a second prepare_netlist_structs() is called to name unnamed nets, in this second call + * print_erc must be set to 0 to avoid double erc printing + */ + print_erc = (xctx->netlist_count == 0 || startlevel < xctx->currsch) && for_netlist; + for (i=0;isym)->type); + if(print_erc && (!inst[i].instname || !inst[i].instname[0]) && + !get_tok_value((inst[i].ptr+ xctx->sym)->templ, "name", 0)[0] + ) { + char str[2048]; + if( type && + strcmp(type, "package") && + strcmp(type, "port_attributes") && + strcmp(type, "architecture") && + strcmp(type, "arch_declarations") && + strcmp(type, "attributes") && + strcmp(type, "netlist_options") && + strcmp(type, "use")) { + my_snprintf(str, S(str), "instance: %d (%s): no name attribute set", i, inst[i].name); + statusmsg(str,2); + inst[i].color = -PINLAYER; + xctx->hilight_nets=1; + } + } + if(print_erc && (!type || !type[0]) ) { + char str[2048]; + my_snprintf(str, S(str), "Symbol: %s: no type attribute set", inst[i].name); + statusmsg(str,2); + inst[i].color = -PINLAYER; + xctx->hilight_nets=1; + } + if(type && inst[i].node && IS_LABEL_OR_PIN(type) ) { /* instance must have a pin! */ + if(for_netlist>0) { + /* 20150918 skip labels / pins if ignore property specified on instance */ + if( xctx->netlist_type == CAD_VERILOG_NETLIST && + strcmp(get_tok_value(inst[i].prop_ptr,"verilog_ignore",0),"true")==0 ) continue; + if( xctx->netlist_type == CAD_SPICE_NETLIST && + strcmp(get_tok_value(inst[i].prop_ptr,"spice_ignore",0),"true")==0 ) continue; + if( xctx->netlist_type == CAD_VHDL_NETLIST && + strcmp(get_tok_value(inst[i].prop_ptr,"vhdl_ignore",0),"true")==0 ) continue; + if( xctx->netlist_type == CAD_TEDAX_NETLIST && + strcmp(get_tok_value(inst[i].prop_ptr,"tedax_ignore",0),"true")==0 ) continue; + } + port=0; + my_strdup2(249, &dir, ""); + if(strcmp(type,"label")) { /* instance is a port (not a label) */ + port=1; + /* 20071204 only define a dir property if instance is not a label */ + if(for_netlist) + my_strdup2(250, &dir, get_tok_value( (inst[i].ptr+ xctx->sym)->rect[PINLAYER][0].prop_ptr, "dir",0)); + } + else { + /* handle global nodes (global=1 set as symbol property) 28032003 */ + my_strdup(251, &global_node,get_tok_value((inst[i].ptr+ xctx->sym)->prop_ptr,"global",0)); + /*20071204 if instance is a label dont define a dir property for more precise erc checking */ + } + /* obtain ipin/opin/label signal type (default: std_logic) */ + if(for_netlist) { + my_strdup(258, &sig_type,get_tok_value(inst[i].prop_ptr,"sig_type",0)); + my_strdup(259, &verilog_type,get_tok_value(inst[i].prop_ptr,"verilog_type",0)); + my_strdup(260, &value,get_tok_value(inst[i].prop_ptr,"value",0)); + my_strdup(261, &class,get_tok_value(inst[i].prop_ptr,"class",0)); + } + my_strdup(262, &inst[i].node[0], inst[i].lab); + if(!(inst[i].node[0])) { + my_strdup(65, &inst[i].node[0], get_tok_value((inst[i].ptr+ xctx->sym)->templ, "lab",0)); + dbg(1, "prepare_netlist_structs(): no lab attr on instance, pick from symbol: %s\n", inst[i].node[0]); + } + /* handle global nodes (global=1 set as symbol property) 28032003 */ + if(!strcmp(type,"label") && global_node && !strcmp(global_node, "true")) { + dbg(1, "prepare_netlist_structs(): global node: %s\n",inst[i].node[0]); + record_global_node(1,NULL, inst[i].node[0]); + } + + /* do not count multiple labels/pins with same name */ + bus_node_hash_lookup(inst[i].node[0], /* insert node in hash table */ + dir, XINSERT, port, sig_type, verilog_type, value, class); + + dbg(2, "prepare_netlist_structs(): pin=%s\n", + get_tok_value( (inst[i].ptr+ xctx->sym)->rect[PINLAYER][0].prop_ptr, "name",0)); + dbg(2, "prepare_netlist_structs(): dir=%s\n", + get_tok_value( (inst[i].ptr+ xctx->sym)->rect[PINLAYER][0].prop_ptr, "dir",0)); + + /* name nets that touch ioin opin alias instances */ + get_inst_pin_coord(i, 0, &x0, &y0); + get_square(x0, y0, &sqx, &sqy); + if(inst[i].node[0]) for(wptr = xctx->wire_spatial_table[sqx][sqy]; wptr; wptr = wptr->next) + { + if(touch(xctx->wire[wptr->n].x1, xctx->wire[wptr->n].y1, + xctx->wire[wptr->n].x2, xctx->wire[wptr->n].y2, x0,y0)) + { + /* short circuit check */ + if(for_netlist>0) signal_short(xctx->wire[wptr->n].node, inst[i].node[0]); + my_strdup(263, &xctx->wire[wptr->n].node, inst[i].node[0]); + my_strdup(264, &xctx->wire[wptr->n].prop_ptr, + subst_token(xctx->wire[wptr->n].prop_ptr, "lab", xctx->wire[wptr->n].node)); + wirecheck(wptr->n); + } + } + } /* if(type && ... */ + } /* for(i=0;iwires;i++) + { + if(xctx->wire[i].node == NULL) + { + set_unnamed_net(i); + } + } +} + +static void reset_node_data_and_rehash(int for_netlist) +{ + int i,j, rects; + xInstance * const inst = xctx->inst; + int const instances = xctx->instances; + + /* reset wire & inst node labels */ + dbg(2, "prepare_netlist_structs(): rehashing wires and instance pins in spatial hash table\n"); + hash_wires(); + for (i=0;isym)->rects[PINLAYER] + + (inst[i].ptr+ xctx->sym)->rects[GENERICLAYER]; + if(rects > 0) + { + inst[i].node = my_malloc(247, sizeof(char *) * rects); + for (j=0;jwire; + xInstance * const inst = xctx->inst; + int changed = 0; + + pt_symbol = my_calloc(973, xctx->symbols, sizeof(int)); + symtable = my_calloc(1581, xctx->symbols, sizeof(int)); + /* we can not loop over xctx->symbols since we keep symbols of parent circuit while netlisting */ + for(i = 0; i < xctx->instances; i++) { + k = inst[i].ptr; + if( k < 0 || symtable[k] ) continue; + symtable[k] =1; + dbg(1, "name_pass_through_nets(): inst=%s sym=%s\n", inst[i].instname, xctx->sym[k].name); + int_hash_init(&table, 37); + for(j = 0; j < xctx->sym[k].rects[PINLAYER]; j++) { + const char *pin_name = get_tok_value(xctx->sym[k].rect[PINLAYER][j].prop_ptr, "name", 0); + if(int_hash_lookup(&table, pin_name, j, XINSERT_NOREPLACE)) { + dbg(1, " pass thru symbol found\n"); + pt_symbol[k] = 1; + there_are_pt = 1; + } + } + int_hash_free(&table); + if(pt_symbol[k]) dbg(1, "duplicated pins: %s\n", xctx->sym[i].name); + } + my_free(831, &symtable); + if(!there_are_pt) { /* nothing to do: no pass through symbols */ + my_free(832, &pt_symbol); + return; + } + dbg(0, "\nname_pass_through_nets() start...\n"); + + do { + dbg(0, "\n\n do loop\n\n"); + changed = 0; + for(i = 0; i < xctx->instances; i++) { + Str_hashtable table = {NULL, 0}; + Str_hashentry *entry; + str_hash_init(&table, 37); + k = inst[i].ptr; + if( k < 0 ) continue; + if(!inst[i].node) continue; + if(!pt_symbol[k]) continue; + for(j = 0; j < xctx->sym[k].rects[PINLAYER]; j++) { + const char *pin_name = get_tok_value(xctx->sym[k].rect[PINLAYER][j].prop_ptr, "name", 0); + get_inst_pin_coord(i, j, &x0, &y0); + get_square(x0, y0, &sqx, &sqy); + for(wptr = xctx->wire_spatial_table[sqx][sqy]; wptr; wptr = wptr->next) { + if(!wire[wptr->n].node) continue; + if(touch(wire[wptr->n].x1, wire[wptr->n].y1, wire[wptr->n].x2, wire[wptr->n].y2, x0,y0)) { + dbg(0, "check inst %s pin %s(%d) wire %d(%s)\n", inst[i].instname, pin_name, j, + wptr->n, wire[wptr->n].node ? wire[wptr->n].node : ""); + str_hash_lookup(&table, pin_name, wire[wptr->n].node, XINSERT_NOREPLACE); + } + } + for(iptr=xctx->instpin_spatial_table[sqx][sqy]; iptr; iptr = iptr ->next) { + if(iptr->n == i || inst[iptr->n].ptr < 0) continue; + if((iptr->x0==x0) && (iptr->y0==y0)) { + my_strdup(1572, &type,(inst[iptr->n].ptr+ xctx->sym)->type); + if(inst[iptr->n].node && type && (IS_LABEL_OR_PIN(type) || pt_symbol[inst[iptr->n].ptr])) { + if(inst[iptr->n].node[iptr->pin]) { + dbg(0, "inst %s pin %s(%d) hash_lookup %s\n", + inst[i].instname, pin_name, j, inst[iptr->n].node[iptr->pin]); + str_hash_lookup(&table, pin_name, inst[iptr->n].node[iptr->pin], XINSERT_NOREPLACE); + } + } + } + } + my_free(1570, &type); + } /* for(j = 0; j < xctx->sym[k].rects[PINLAYER]; j++) */ + + for(j = 0; j < xctx->sym[k].rects[PINLAYER]; j++) { + const char *pin_name = get_tok_value(xctx->sym[k].rect[PINLAYER][j].prop_ptr, "name", 0); + get_inst_pin_coord(i, j, &x0, &y0); + get_square(x0, y0, &sqx, &sqy); + entry = str_hash_lookup(&table, pin_name, NULL, XLOOKUP); + if(!entry) dbg(0, "inst %s pin %s(%d) is unset\n", inst[i].instname, pin_name, j); + if(!entry) continue; + if(!inst[i].node[j]) set_inst_node(i, j, entry->value, for_netlist); + dbg(0, "inst %s pin %s(%d) <-- %s\n", inst[i].instname, pin_name, j, entry->value); + for(wptr = xctx->wire_spatial_table[sqx][sqy]; wptr; wptr = wptr->next) { + if(touch(wire[wptr->n].x1, wire[wptr->n].y1, wire[wptr->n].x2, wire[wptr->n].y2, x0,y0)) { + if(!wire[wptr->n].node) { + dbg(0, "wire %d <-- inst %s pin %s net %s\n", wptr->n, inst[i].instname, pin_name, entry->value); + my_strdup(1565, &wire[wptr->n].node, entry->value); + my_strdup(834, &wire[wptr->n].prop_ptr, + subst_token(wire[wptr->n].prop_ptr, "lab", wire[wptr->n].node)); + wirecheck(wptr->n); /* recursive check */ + changed = 1; + } else { + dbg(0, "wire %d has already node: %s\n", wptr->n, wire[wptr->n].node); + } + } + } /* for(wptr=...) */ + for(iptr=xctx->instpin_spatial_table[sqx][sqy]; iptr; iptr= iptr->next) { + if(iptr->n == i || inst[iptr->n].ptr < 0) continue; + my_strdup(1569, &type,(inst[i].ptr+ xctx->sym)->type); + if(type && !IS_LABEL_OR_PIN(type) && pt_symbol[iptr->n] && inst[iptr->n].node) { + if((iptr->x0==x0) && (iptr->y0==y0)) { + if(!inst[iptr->n].node[iptr->pin]) { + set_inst_node(iptr->n, iptr->pin, entry->value, for_netlist); + } else { + dbg(0, "inst %s pin %s(%d) has already node: %s\n", + inst[iptr->n].instname, pin_name, iptr->pin, inst[iptr->n].node[iptr->pin]); + } + } + } + } + } /* for(j = 0; j < xctx->sym[k].rects[PINLAYER]; j++) */ + str_hash_free(&table); + } /* for(i = 0; i < xctx->instances; i++) */ + } while(changed); + my_free(833, &pt_symbol); +} void prepare_netlist_structs(int for_netlist) { - xRect *rct; - char tmp_str[30]; /* overflow safe */ char nn[PATH_MAX+30]; - double x0, y0; - short rot = 0; - short flip = 0; - int sqx, sqy; - int port; - int touches=0; - int touches_unnamed=0; - double rx1,ry1; - Wireentry *wptr; - Instpinentry *iptr; - int i,j, rects, generic_rects; - char *dir=NULL; - char *type=NULL; - char *sig_type=NULL; - char *verilog_type=NULL; - char *value=NULL; - char *class=NULL; - char *global_node=NULL; - int inst_mult, pin_mult; - int print_erc; - static int startlevel = 0; /* safe to keep even with multiple schematic windows, netlist is not interruptable */ - xInstance * const inst = xctx->inst; - int const instances = xctx->instances; - if (for_netlist>0 && xctx->prep_net_structs) return; - else if (!for_netlist && xctx->prep_hi_structs) return; + if(for_netlist>0 && xctx->prep_net_structs) return; + else if(!for_netlist && xctx->prep_hi_structs) return; /* delete instance pins spatial hash, wires spatial hash, node_hash, wires and inst nodes.*/ - delete_netlist_structs(); - free_simdata(); /* invalidate simulation cache */ - dbg(1, "prepare_netlist_structs(): extraction: %s\n", xctx->sch[xctx->currsch]); - if(xctx->netlist_count == 0 ) startlevel = xctx->currsch; - /* print_erc is 1 the first time prepare_netlist_structs() is called on top level while - * doing the netlist, when netlist of sub blocks is completed and toplevel is reloaded - * a second prepare_netlist_structs() is called to name unnamed nets, in this second call - * print_erc must be set to 0 to avoid double erc printing - */ - print_erc = (xctx->netlist_count == 0 || startlevel < xctx->currsch) && for_netlist; - if (for_netlist) { + if(for_netlist) { my_snprintf(nn, S(nn), "-----------%s", xctx->sch[xctx->currsch]); statusmsg(nn,2); } - /* reset wire & inst node labels */ - dbg(2, "prepare_netlist_structs(): rehashing wires and instance pins in spatial hash table\n"); - hash_wires(); - for (i=0;isym)->rects[PINLAYER] + - (inst[i].ptr+ xctx->sym)->rects[GENERICLAYER]; - if (rects > 0) - { - inst[i].node = my_malloc(247, sizeof(char *) * rects); - for (j=0;jsym)->type); - if(print_erc && (!inst[i].instname || !inst[i].instname[0]) && - !get_tok_value((inst[i].ptr+ xctx->sym)->templ, "name", 0)[0] - ) { - char str[2048]; - if( type && - strcmp(type, "package") && - strcmp(type, "port_attributes") && - strcmp(type, "architecture") && - strcmp(type, "arch_declarations") && - strcmp(type, "attributes") && - strcmp(type, "netlist_options") && - strcmp(type, "use")) { - my_snprintf(str, S(str), "instance: %d (%s): no name attribute set", i, inst[i].name); - statusmsg(str,2); - inst[i].color = -PINLAYER; - xctx->hilight_nets=1; - } - } - if(print_erc && (!type || !type[0]) ) { - char str[2048]; - my_snprintf(str, S(str), "Symbol: %s: no type attribute set", inst[i].name); - statusmsg(str,2); - inst[i].color = -PINLAYER; - xctx->hilight_nets=1; - } - if(type && inst[i].node && IS_LABEL_OR_PIN(type) ) { /* instance must have a pin! */ - if (for_netlist>0) { - /* 20150918 skip labels / pins if ignore property specified on instance */ - if( xctx->netlist_type == CAD_VERILOG_NETLIST && - strcmp(get_tok_value(inst[i].prop_ptr,"verilog_ignore",0),"true")==0 ) continue; - if( xctx->netlist_type == CAD_SPICE_NETLIST && - strcmp(get_tok_value(inst[i].prop_ptr,"spice_ignore",0),"true")==0 ) continue; - if( xctx->netlist_type == CAD_VHDL_NETLIST && - strcmp(get_tok_value(inst[i].prop_ptr,"vhdl_ignore",0),"true")==0 ) continue; - if( xctx->netlist_type == CAD_TEDAX_NETLIST && - strcmp(get_tok_value(inst[i].prop_ptr,"tedax_ignore",0),"true")==0 ) continue; - } - port=0; - if (strcmp(type,"label")) { /* instance is a port (not a label) */ - port=1; - /* 20071204 only define a dir property if instance is not a label */ - if (!for_netlist) my_strdup(249, &dir, ""); - else - my_strdup(250, &dir, get_tok_value( (inst[i].ptr+ xctx->sym)->rect[PINLAYER][0].prop_ptr, "dir",0)); - } - else { - /* handle global nodes (global=1 set as symbol property) 28032003 */ - my_strdup(251, &global_node,get_tok_value((inst[i].ptr+ xctx->sym)->prop_ptr,"global",0)); - /*20071204 if instance is a label dont define a dir property for more precise erc checking */ - my_strdup(252, &dir,"none"); - } - - if (!dir) my_strdup(253, &dir,"none"); /* 20100422, define dir if not alrerady defined by */ - /* previous code, to avoid nasty segfaults if pins not correctly defined */ - - /* obtain ipin/opin/label signal type (default: std_logic) */ - if (!for_netlist) { - my_free(831, &sig_type); - my_free(832, &verilog_type); - my_free(833, &value); - my_free(834, &class); - } else { - my_strdup(258, &sig_type,get_tok_value(inst[i].prop_ptr,"sig_type",0)); - my_strdup(259, &verilog_type,get_tok_value(inst[i].prop_ptr,"verilog_type",0)); - my_strdup(260, &value,get_tok_value(inst[i].prop_ptr,"value",0)); - my_strdup(261, &class,get_tok_value(inst[i].prop_ptr,"class",0)); - } - my_strdup(262, &inst[i].node[0], inst[i].lab); - if (!(inst[i].node[0])) { - my_strdup(65, &inst[i].node[0], get_tok_value((inst[i].ptr+ xctx->sym)->templ, "lab",0)); - dbg(1, "prepare_netlist_structs(): no lab attr on instance, pick from symbol: %s\n", inst[i].node[0]); - } - /* handle global nodes (global=1 set as symbol property) 28032003 */ - if (!strcmp(type,"label") && global_node && !strcmp(global_node, "true")) { - dbg(1, "prepare_netlist_structs(): global node: %s\n",inst[i].node[0]); - record_global_node(1,NULL, inst[i].node[0]); - } - - /* do not count multiple labels/pins with same name */ - bus_node_hash_lookup(inst[i].node[0], /* insert node in hash table */ - dir, XINSERT, port, sig_type, verilog_type, value, class); - - dbg(2, "prepare_netlist_structs(): pin=%s\n", - get_tok_value( (inst[i].ptr+ xctx->sym)->rect[PINLAYER][0].prop_ptr, "name",0)); - dbg(2, "prepare_netlist_structs(): dir=%s\n", - get_tok_value( (inst[i].ptr+ xctx->sym)->rect[PINLAYER][0].prop_ptr, "dir",0)); - - /* name nets that touch ioin opin alias instances */ - rct=(inst[i].ptr+ xctx->sym)->rect[PINLAYER]; - x0=(rct[0].x1+rct[0].x2)/2; - y0=(rct[0].y1+rct[0].y2)/2; - rot=inst[i].rot; - flip=inst[i].flip; - ROTATION(rot, flip, 0.0,0.0,x0,y0,rx1,ry1); - x0=inst[i].x0+rx1; - y0=inst[i].y0+ry1; - get_square(x0, y0, &sqx, &sqy); - wptr=xctx->wire_spatial_table[sqx][sqy]; - if (inst[i].node[0]) while(wptr) - { - if (touch(xctx->wire[wptr->n].x1, xctx->wire[wptr->n].y1, - xctx->wire[wptr->n].x2, xctx->wire[wptr->n].y2, x0,y0)) - { - /* short circuit check */ - if (for_netlist>0) signal_short(xctx->wire[wptr->n].node, inst[i].node[0]); - my_strdup(263, &xctx->wire[wptr->n].node, inst[i].node[0]); - my_strdup(264, &xctx->wire[wptr->n].prop_ptr, - subst_token(xctx->wire[wptr->n].prop_ptr, "lab", xctx->wire[wptr->n].node)); - wirecheck(wptr->n); - } - wptr=wptr->next; - } - } /* if(type && ... */ - } /* for(i=0;isch[xctx->currsch]); + delete_netlist_structs(); + free_simdata(); /* invalidate simulation cache */ + reset_node_data_and_rehash(for_netlist); get_unnamed_node(0,0,0); /*initializes node multiplicity data struct */ - for (i=0;iwires;i++) - { - if(xctx->wire[i].node == NULL) - { - my_snprintf(tmp_str, S(tmp_str), "#net%d", get_unnamed_node(1,0,0)); + name_nodes_of_pins_labels_and_attached_nets(for_netlist); + /* name_nets_from_pass_through_syms(for_netlist); */ + name_unlabeled_nets(); + name_pass_through_nets(for_netlist); + name_generics(for_netlist); + name_non_label_inst_pins(for_netlist); - /* JL avoid autonamed nets clash with user defined 'net#' names */ - while (bus_node_hash_lookup(&tmp_str[1], "", XLOOKUP, 0, "", "", "", "")!=NULL) - my_snprintf(tmp_str, S(tmp_str), "#net%d", get_unnamed_node(1, 0, 0)); - - my_strdup(265, &xctx->wire[i].node , tmp_str); - my_strdup(266, &xctx->wire[i].prop_ptr, - subst_token(xctx->wire[i].prop_ptr, "lab", xctx->wire[i].node)); - /* insert unnamed wire name in hash table */ - bus_node_hash_lookup(xctx->wire[i].node,"", XINSERT, 0,"","","",""); - wirecheck(i); - } - } - - name_pass_through_nets(for_netlist); /* name nets that are attached to symbols with duplicated pins. */ - - /* NAME GENERICS */ - - /* name generic pins from attached labels */ - dbg(2, "prepare_netlist_structs(): naming generics from attached labels\n"); - if(for_netlist) for (i=0;isym)->type); - if (type && !IS_LABEL_OR_PIN(type) ) { - if ((generic_rects = (inst[i].ptr+ xctx->sym)->rects[GENERICLAYER]) > 0) - { - rects = (inst[i].ptr+ xctx->sym)->rects[PINLAYER]; - for (j=rects;jsym)->rect[GENERICLAYER]; - x0=(rct[j-rects].x1+rct[j-rects].x2)/2; - y0=(rct[j-rects].y1+rct[j-rects].y2)/2; - rot=inst[i].rot; - flip=inst[i].flip; - ROTATION(rot, flip, 0.0,0.0,x0,y0,rx1,ry1); - x0=inst[i].x0+rx1; - y0=inst[i].y0+ry1; - get_square(x0, y0, &sqx, &sqy); - - iptr=xctx->instpin_spatial_table[sqx][sqy]; - while (iptr) - { - if (iptr->n == i) - { - iptr=iptr->next; - continue; - } - if ((iptr->x0==x0) && (iptr->y0==y0)) - { - if ((inst[iptr->n].ptr+ xctx->sym)->type && inst[iptr->n].node[iptr->pin] != NULL && - !strcmp((inst[iptr->n].ptr+ xctx->sym)->type, "label")) - { - dbg(2, "prepare_netlist_structs(): naming generic %s\n", - inst[iptr->n].node[iptr->pin]); - - my_strdup(268, &inst[i].node[j], get_tok_value(inst[iptr->n].prop_ptr,"value",0) ); - - /*my_strdup(269, &inst[i].node[j], inst[iptr->n].node[iptr->pin] ); */ - - if (!for_netlist) { - my_strdup(270, &sig_type,""); - bus_node_hash_lookup(inst[iptr->n].node[iptr->pin],"none", - XINSERT, 1, sig_type,"", "",""); - } else { - my_strdup(271, &sig_type,get_tok_value( - (inst[i].ptr+ xctx->sym)->rect[GENERICLAYER][j-rects].prop_ptr, "sig_type",0)); - - /* insert generic label in hash table as a port so it will not */ - /* be declared as a signal in the vhdl netlist. this is a workaround */ - /* that should be fixed 25092001 */ - bus_node_hash_lookup(inst[iptr->n].node[iptr->pin], - get_tok_value((inst[i].ptr+ xctx->sym)->rect[GENERICLAYER][j-rects].prop_ptr, "dir",0), - XINSERT, 1, sig_type,"", "",""); - } - } /* end if(inst[iptr->n].node[iptr->pin] != NULL) */ - } /* end if( (iptr->x0==x0) && (iptr->y0==y0) ) */ - iptr=iptr->next; - } - } /* end for(j=0;j0) */ - } /* end if(type not a label nor pin)... */ - } /* end for(i...) */ - - /* END NAME GENERICS */ - - /* name instance pins of non (label,pin) instances */ - dbg(2, "prepare_netlist_structs(): assigning node names on instance pins\n"); - for (i=0;isym)->type); - if (type && !IS_LABEL_OR_PIN(type) ) { - if ((rects = (inst[i].ptr+ xctx->sym)->rects[PINLAYER]) > 0) - { - for (j=0;jsym)->rect[PINLAYER]; - x0=(rct[j].x1+rct[j].x2)/2; - y0=(rct[j].y1+rct[j].y2)/2; - rot=inst[i].rot; - flip=inst[i].flip; - ROTATION(rot, flip, 0.0,0.0,x0,y0,rx1,ry1); - x0=inst[i].x0+rx1; - y0=inst[i].y0+ry1; - get_square(x0, y0, &sqx, &sqy); - /* name instance nodes that touch named nets */ - wptr=xctx->wire_spatial_table[sqx][sqy]; - dbg(2, "prepare_netlist_structs(): from attached nets\n"); - while (wptr) - { - if (touch(xctx->wire[wptr->n].x1, xctx->wire[wptr->n].y1, - xctx->wire[wptr->n].x2, xctx->wire[wptr->n].y2, x0,y0)) - { - - /* short circuit check */ - if (touches) - { - if (for_netlist>0) signal_short(inst[i].node[j], xctx->wire[wptr->n].node); - } - if (!touches) - { - my_strdup(273, &inst[i].node[j], xctx->wire[wptr->n].node ); - bus_node_hash_lookup(inst[i].node[j], - get_tok_value( (inst[i].ptr+ xctx->sym)->rect[PINLAYER][j].prop_ptr, "dir",0), - XINSERT, 0,"","","",""); - - if (xctx->wire[wptr->n].node[0]=='#') /* unnamed node, update its multiplicity */ - { - expandlabel(get_tok_value( - (inst[i].ptr+ xctx->sym)->rect[PINLAYER][j].prop_ptr,"name",0),&pin_mult); - - get_unnamed_node(2, pin_mult * inst_mult, atoi((inst[i].node[j])+4) ); - } - } /* end if(!touches) */ - touches=1; - } - wptr=wptr->next; - } - - dbg(2, "prepare_netlist_structs(): from other instances\n"); - touches_unnamed=0; - iptr=xctx->instpin_spatial_table[sqx][sqy]; - while (iptr) - { - if (iptr->n == i) - { - iptr=iptr->next; - continue; - } - if ((iptr->x0==x0) && (iptr->y0==y0)) - { - if (inst[iptr->n].node[iptr->pin] != NULL) - { - /* short circuit check */ - if (touches) - { - if (for_netlist>0) signal_short(inst[i].node[j], inst[iptr->n].node[iptr->pin]); - } - if (!touches) - { - my_strdup(274, &inst[i].node[j], inst[iptr->n].node[iptr->pin] ); - if (!for_netlist) { - bus_node_hash_lookup(inst[i].node[j],"none", XINSERT, 0,"","","",""); - } else { - bus_node_hash_lookup(inst[i].node[j], - get_tok_value( (inst[i].ptr+ xctx->sym)->rect[PINLAYER][j].prop_ptr, "dir",0), - XINSERT, 0,"","","",""); - } - if ((inst[i].node[j])[0] == '#') - { - expandlabel(get_tok_value( - (inst[i].ptr+ xctx->sym)->rect[PINLAYER][j].prop_ptr,"name",0),&pin_mult ); - /* done at beginning of for(i) loop 20171210 */ - /* expandlabel(get_tok_value( */ - /* inst[i].prop_ptr,"name",0), &inst_mult); */ - get_unnamed_node(2, pin_mult * inst_mult, atoi((inst[i].node[j])+4)); - } - } - touches=1; - } /* end if(inst[iptr->n].node[iptr->pin] != NULL) */ - else /* touches instance with unnamed pins */ - { - touches_unnamed=1; - } - } /* end if( (iptr->x0==x0) && (iptr->y0==y0) ) */ - iptr=iptr->next; - } - - /* pin did not touch named pins or nets so we name it now */ - dbg(2, "prepare_netlist_structs(): naming the other pins\n"); - if (!touches) { /* pin does not touch any other instance pin with non NULL node[] field ...*/ - if (touches_unnamed) /* ... but touches some other instance pin, so create unnamed net */ - { - expandlabel(get_tok_value( - (inst[i].ptr+ xctx->sym)->rect[PINLAYER][j].prop_ptr,"name",0), &pin_mult); - /* done at beginning of for(i) loop 20171210 */ - /* expandlabel(get_tok_value( */ - /* inst[i].prop_ptr,"name",0), &inst_mult); */ - my_snprintf( tmp_str, S(tmp_str), "#net%d", get_unnamed_node(1, pin_mult * inst_mult, 0)); - my_strdup(275, &inst[i].node[j], tmp_str ); - if (!for_netlist) { - bus_node_hash_lookup(inst[i].node[j],"none", XINSERT, 0,"","","",""); - } else { - bus_node_hash_lookup(inst[i].node[j], - get_tok_value( (inst[i].ptr+ xctx->sym)->rect[PINLAYER][j].prop_ptr, "dir",0), - XINSERT, 0,"","","",""); - } - } - } - } /* end for(j=0;j0) */ - } /* end if(type not a label nor pin)... */ - } /* end for(i...) */ - /*---------------------- */ rebuild_selected_array(); - if (for_netlist>0) { + if(for_netlist>0) { xctx->prep_net_structs=1; xctx->prep_hi_structs=1; } else xctx->prep_hi_structs=1; - my_free(835, &dir); - my_free(836, &type); - my_free(837, &sig_type); - my_free(838, &verilog_type); - my_free(839, &value); - my_free(840, &class); - my_free(841, &global_node); dbg(1, "prepare_netlist_structs(): returning\n"); /* avoid below call: it in turn calls prepare_netlist_structs(), too many side effects */ /* propagate_hilights(1, 0, XINSERT_NOREPLACE);*/ } +void delete_inst_node(int i) +{ + int j, rects; + if( xctx->inst[i].ptr == -1 || !xctx->inst[i].node) return; + rects = (xctx->inst[i].ptr+ xctx->sym)->rects[PINLAYER] + + (xctx->inst[i].ptr+ xctx->sym)->rects[GENERICLAYER]; + if( rects > 0 ) + { + for(j=0;j< rects ;j++) + my_free(849, &xctx->inst[i].node[j]); + my_free(850, &xctx->inst[i].node ); + } +} + +void delete_netlist_structs(void) +{ + int i; + /* erase node data structures */ + dbg(1, "delete_netlist_structs(): begin erasing\n"); + for(i=0;iinstances;i++) + { + delete_inst_node(i); + } + for(i=0;iwires;i++) + { + my_free(851, &xctx->wire[i].node); + } + /* erase inst and wire topological hash tables */ + del_inst_pin_table(); + node_hash_free(); + dbg(1, "delete_netlist_structs(): end erasing\n"); + xctx->prep_net_structs=0; + xctx->prep_hi_structs=0; +} + int warning_overlapped_symbols(int sel) { int i; @@ -1547,38 +1673,3 @@ int sym_vs_sch_pins() while(xctx->symbols > n_syms) remove_symbol(xctx->symbols - 1); return 0; } - -void delete_inst_node(int i) -{ - int j, rects; - if( xctx->inst[i].ptr == -1 || !xctx->inst[i].node) return; - rects = (xctx->inst[i].ptr+ xctx->sym)->rects[PINLAYER] + - (xctx->inst[i].ptr+ xctx->sym)->rects[GENERICLAYER]; - if( rects > 0 ) - { - for(j=0;j< rects ;j++) - my_free(849, &xctx->inst[i].node[j]); - my_free(850, &xctx->inst[i].node ); - } -} - -void delete_netlist_structs(void) -{ - int i; - /* erase node data structures */ - dbg(1, "delete_netlist_structs(): begin erasing\n"); - for(i=0;iinstances;i++) - { - delete_inst_node(i); - } - for(i=0;iwires;i++) - { - my_free(851, &xctx->wire[i].node); - } - /* erase inst and wire topological hash tables */ - del_inst_pin_table(); - node_hash_free(); - dbg(1, "delete_netlist_structs(): end erasing\n"); - xctx->prep_net_structs=0; - xctx->prep_hi_structs=0; -} diff --git a/src/node_hash.c b/src/node_hash.c index 3ac58a39..2c6badee 100644 --- a/src/node_hash.c +++ b/src/node_hash.c @@ -43,9 +43,11 @@ static Node_hashentry *node_hash_lookup(const char *token, const char *dir,int w dbg(3, "node_hash_lookup(): called with: %s dir=%s what=%d port=%d\n", token, dir, what, port); d.in=d.out=d.inout=0; - if(!strcmp(dir,"in") ) d.in=1; - else if(!strcmp(dir,"out") ) d.out=1; - else if(!strcmp(dir,"inout") ) d.inout=1; + if(dir) { + if(!strcmp(dir,"in") ) d.in=1; + else if(!strcmp(dir,"out") ) d.out=1; + else if(!strcmp(dir,"inout") ) d.inout=1; + } d.port=port; hashcode=str_hash(token); index=hashcode % HASHSIZE; diff --git a/src/select.c b/src/select.c index be6b35a2..855ee951 100644 --- a/src/select.c +++ b/src/select.c @@ -45,18 +45,11 @@ static void check_connected_wire(int stop_at_junction, int n) k = instptr->n; type = (xctx->inst[k].ptr+ xctx->sym)->type; if( type && (IS_LABEL_SH_OR_PIN(type) || !strcmp(type, "probe") || !strcmp(type, "ngprobe"))) { - double rx1, ry1, x0, y0; - int rot, flip; + double x0, y0; xRect *rct; rct=(xctx->inst[k].ptr+ xctx->sym)->rect[PINLAYER]; if(rct) { - x0=(rct[0].x1+rct[0].x2)/2; - y0=(rct[0].y1+rct[0].y2)/2; - rot=xctx->inst[k].rot; - flip=xctx->inst[k].flip; - ROTATION(rot, flip, 0.0,0.0,x0,y0,rx1,ry1); - x0=xctx->inst[k].x0+rx1; - y0=xctx->inst[k].y0+ry1; + get_inst_pin_coord(k, 0, &x0, &y0); touches = touch(wire[n].x1, wire[n].y1, wire[n].x2, wire[n].y2, x0, y0); if(touches) { xctx->need_reb_sel_arr=1; @@ -106,19 +99,13 @@ void select_connected_wires(int stop_at_junction) case ELEMENT: type = (xctx->inst[i].ptr+ xctx->sym)->type; if( type && (IS_LABEL_SH_OR_PIN(type) || !strcmp(type, "probe") || !strcmp(type, "ngprobe"))) { - double rx1, ry1, x0, y0; - int rot, flip, sqx, sqy; + double x0, y0; + int sqx, sqy; xRect *rct; Wireentry *wptr; rct = (xctx->inst[i].ptr+ xctx->sym)->rect[PINLAYER]; if(rct) { - x0 = (rct[0].x1 + rct[0].x2) / 2; - y0 = (rct[0].y1 + rct[0].y2) / 2; - rot = xctx->inst[i].rot; - flip = xctx->inst[i].flip; - ROTATION(rot, flip, 0.0,0.0,x0,y0,rx1,ry1); - x0 = xctx->inst[i].x0+rx1; - y0 = xctx->inst[i].y0+ry1; + get_inst_pin_coord(i, 0, &x0, &y0); get_square(x0, y0, &sqx, &sqy); wptr = xctx->wire_spatial_table[sqx][sqy]; while (wptr) { diff --git a/src/xschem.h b/src/xschem.h index 26f87b3b..24facbe1 100644 --- a/src/xschem.h +++ b/src/xschem.h @@ -1122,6 +1122,7 @@ extern int text_bbox(const char * str,double xscale, double yscale, extern int get_color(int value); extern void incr_hilight_color(void); extern void hash_inst(int what, int n); +extern void get_inst_pin_coord(int i, int j, double *x, double *y); extern void del_inst_table(void); extern void hash_wires(void); extern void hash_wire(int what, int n, int incremental); diff --git a/xschem_library/examples/doublepin.sch b/xschem_library/examples/doublepin.sch index 846d667e..dcc2b076 100644 --- a/xschem_library/examples/doublepin.sch +++ b/xschem_library/examples/doublepin.sch @@ -21,7 +21,7 @@ end} S {} E {} C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"} -C {ipin.sym} 210 -220 0 0 {name=p1 lab=A} +C {ipin.sym} 210 -220 0 0 {name=p1 lab=A[3:0]} C {ipin.sym} 210 -190 0 0 {name=p3 lab=B} C {opin.sym} 520 -240 0 0 {name=p4 lab=Z} C {ipin.sym} 210 -260 0 0 {name=p5 lab=RST} diff --git a/xschem_library/examples/doublepin.sym b/xschem_library/examples/doublepin.sym index efb07758..b2d052d6 100644 --- a/xschem_library/examples/doublepin.sym +++ b/xschem_library/examples/doublepin.sym @@ -1,7 +1,8 @@ -v {xschem version=3.0.0 file_version=1.2 } +v {xschem version=3.1.0 file_version=1.2 +} G {} K {type=subcircuit -format="@name @@A @@B @@CK @@RST @@Z @symname" +format="@name @@A[3:0] @@B @@CK @@RST @@Z @symname" template="name=x1" } V {} @@ -38,10 +39,10 @@ L 4 135 10 140 5 {} L 4 135 10 140 15 {} L 4 135 45 140 50 {} L 4 135 55 140 50 {} -B 5 -152.5 -12.5 -147.5 -7.5 {name=A dir=in } +B 5 -152.5 -12.5 -147.5 -7.5 {name=A[3:0] dir=in } B 5 -152.5 7.5 -147.5 12.5 {name=B dir=in } B 5 147.5 47.5 152.5 52.5 {name=Z dir=out } -B 5 147.5 -12.5 152.5 -7.5 {name=A dir=in } +B 5 147.5 -12.5 152.5 -7.5 {name=A[3:0] dir=in } B 5 -152.5 -32.5 -147.5 -27.5 {name=CK dir=in } B 5 147.5 -32.5 152.5 -27.5 {name=CK dir=in } B 5 -152.5 -52.5 -147.5 -47.5 {name=RST dir=in } @@ -49,8 +50,8 @@ B 5 147.5 -52.5 152.5 -47.5 {name=RST dir=in } B 5 147.5 7.5 152.5 12.5 {name=B dir=in } T {@symname} -58.5 -6 0 0 0.3 0.3 {} T {@name} 105 -72 0 0 0.2 0.2 {} -T {A} 125 -14 0 1 0.2 0.2 {} -T {A} -125 -14 0 0 0.2 0.2 {} +T {A[3:0]} 125 -14 0 1 0.2 0.2 {} +T {A[3:0]} -125 -14 0 0 0.2 0.2 {} T {Z} 125 46 0 1 0.2 0.2 {} T {B} -125 6 0 0 0.2 0.2 {} T {CK} -125 -34 0 0 0.2 0.2 {} @@ -58,3 +59,12 @@ T {CK} 125 -34 0 1 0.2 0.2 {} T {RST} -125 -54 0 0 0.2 0.2 {} T {RST} 125 -54 0 1 0.2 0.2 {} T {B} 125 6 0 1 0.2 0.2 {} +T {@#6:net_name} -127.5 -61.25 0 0 0.15 0.15 {layer=15} +T {@#4:net_name} -127.5 -41.25 0 0 0.15 0.15 {layer=15} +T {@#0:net_name} -127.5 -21.25 0 0 0.15 0.15 {layer=15} +T {@#1:net_name} -127.5 -1.25 0 0 0.15 0.15 {layer=15} +T {@#7:net_name} 127.5 -61.25 0 1 0.15 0.15 {layer=15} +T {@#5:net_name} 127.5 -41.25 0 1 0.15 0.15 {layer=15} +T {@#3:net_name} 127.5 -21.25 0 1 0.15 0.15 {layer=15} +T {@#8:net_name} 127.5 -1.25 0 1 0.15 0.15 {layer=15} +T {@#2:net_name} 127.5 38.75 0 1 0.15 0.15 {layer=15} diff --git a/xschem_library/examples/test_doublepin.sch b/xschem_library/examples/test_doublepin.sch index 5b33bf33..34806e3f 100644 --- a/xschem_library/examples/test_doublepin.sch +++ b/xschem_library/examples/test_doublepin.sch @@ -24,21 +24,13 @@ vvss vss 0 dc 0 .tran 1n 200n} E {} -T {OK!} 500 -1020 0 0 1 1 {layer=4} -T {OK!} 500 -1250 0 0 1 1 {layer=4} -T {OK!} 500 -1480 0 0 1 1 {layer=4} T {Spice netlist allows duplicated pins on symbols} 50 -1570 0 0 1 1 {} -T {OK!} 500 -790 0 0 1 1 {layer=4} -T {OK!} 500 -580 0 0 1 1 {layer=4} -T {OK!} 1320 -1160 0 0 1 1 {layer=4} -T {OK!} 1320 -1430 0 0 1 1 {layer=4} -T {OK!} 500 -350 0 0 1 1 {layer=4} N 480 -930 630 -930 { lab=RRSSTT} N 480 -910 630 -910 { lab=CCKK} N 480 -890 630 -890 { -lab=AA} +lab=AA[3:0]} N 480 -870 630 -870 { lab=BB} N 480 -830 510 -830 { @@ -58,29 +50,29 @@ lab=RRSSTT} N 480 -1370 630 -1370 { lab=CCKK} N 480 -1350 630 -1350 { -lab=AA} +lab=AA[3:0]} N 480 -1330 630 -1330 { lab=BB} N 480 -720 660 -720 { -lab=RRSSTT} +lab=#net1} N 480 -700 660 -700 { -lab=CCKK} +lab=#net2} N 480 -680 660 -680 { -lab=AA} +lab=#net3} N 480 -660 660 -660 { -lab=BB} +lab=#net4} N 480 -620 510 -620 { lab=ZZ7} N 630 -620 660 -620 { lab=ZZ8} N 960 -720 1080 -720 { -lab=RRSSTT} +lab=#net5} N 960 -700 1080 -700 { -lab=CCKK} +lab=#net6} N 960 -680 1080 -680 { -lab=AA} +lab=#net7} N 960 -660 1080 -660 { -lab=BB} +lab=#net8} N 1380 -620 1410 -620 { lab=ZZ9} N 480 -510 660 -510 { @@ -95,136 +87,215 @@ N 480 -410 510 -410 { lab=ZZ12} N 630 -410 660 -410 { lab=ZZ11} -N 960 -510 1080 -510 { -lab=#net13} -N 960 -490 1080 -490 { -lab=#net14} -N 960 -470 1080 -470 { -lab=#net15} -N 960 -450 1080 -450 { -lab=#net16} -N 1380 -410 1410 -410 { +N 1260 -410 1290 -410 { lab=ZZ10} N 1520 -990 1550 -990 { lab=ZZ13} N 1170 -1090 1220 -1090 { -lab=RRSSTT} +lab=#net13} N 1170 -1070 1220 -1070 { -lab=CCKK} +lab=#net14} N 1170 -1050 1220 -1050 { -lab=AA} +lab=#net15} N 1170 -1030 1220 -1030 { -lab=BB} +lab=#net16} N 1190 -1250 1220 -1250 { lab=ZZ14} N 1170 -1350 1220 -1350 { -lab=RRSSTT} +lab=#net17} N 1170 -1330 1220 -1330 { -lab=CCKK} +lab=#net18} N 1170 -1310 1220 -1310 { -lab=AA} +lab=#net19} N 1170 -1290 1220 -1290 { -lab=BB} +lab=#net20} N 480 -280 660 -280 { -lab=#net25} +lab=#net21} N 480 -260 660 -260 { -lab=#net26} +lab=#net22} N 480 -240 660 -240 { -lab=#net27} +lab=#net23} N 480 -220 660 -220 { -lab=#net28} +lab=#net24} N 480 -180 510 -180 { lab=ZZ17} N 630 -180 660 -180 { lab=ZZ16} N 960 -280 1080 -280 { -lab=#net29} +lab=#net25} N 960 -260 1080 -260 { -lab=#net30} +lab=#net26} N 960 -240 1080 -240 { -lab=#net31} +lab=#net27} N 960 -220 1080 -220 { -lab=#net32} +lab=#net28} N 1380 -180 1410 -180 { lab=ZZ15} N 10 -260 40 -260 { -lab=#net33} +lab=#net29} N 120 -260 180 -260 { +lab=#net30} +N 70 -450 100 -450 { +lab=#net31} +N 1260 -510 1440 -510 { +lab=#net32} +N 1260 -490 1440 -490 { +lab=#net33} +N 1260 -470 1440 -470 { lab=#net34} -C {doublepin.sym} 1230 -670 0 0 {name=x9} -C {doublepin.sym} 810 -670 0 1 {name=x8} -C {doublepin.sym} 780 -880 0 0 {name=x2} -C {lab_wire.sym} 550 -890 0 0 {name=l2 sig_type=std_logic lab=AA} +N 1260 -450 1440 -450 { +lab=#net35} +N 1740 -310 1770 -310 { +lab=ZZ18} +N 1740 -410 1740 -310 { +lab=ZZ18} +N 2040 -310 2070 -310 { +lab=ZZ19} +N 2040 -410 2040 -310 { +lab=ZZ19} +N 620 -350 620 -280 { +lab=#net21} +N 620 -350 680 -350 { +lab=#net21} +N 760 -350 810 -350 { +lab=#net36} +N 1110 -920 1260 -920 { +lab=RRSSTT} +N 1110 -900 1260 -900 { +lab=CCKK} +N 1110 -880 1260 -880 { +lab=AA[3:0]} +N 1110 -860 1260 -860 { +lab=BB} +N 1560 -820 1590 -820 { +lab=ZZ20} +N 1560 -920 1760 -920 { +lab=RRSSTT} +N 1560 -900 1760 -900 { +lab=CCKK} +N 1560 -880 1760 -880 { +lab=AA[3:0]} +N 1560 -860 1760 -860 { +lab=BB} +N 1730 -820 1760 -820 { +lab=ZZ21} +N 2060 -880 2180 -880 { +lab=#net37} +N 2060 -860 2180 -860 { +lab=#net38} +N 2060 -900 2180 -900 { +lab=#net39} +N 2060 -920 2180 -920 { +lab=#net40} +C {doublepin.sym} 1230 -670 0 0 {name=x9 +net_name=true} +C {doublepin.sym} 810 -670 0 1 {name=x8 +net_name=true} +C {doublepin.sym} 780 -880 0 0 {name=x2 +net_name=true} +C {lab_wire.sym} 550 -890 0 0 {name=l2 sig_type=std_logic lab=AA[3:0]} C {lab_pin.sym} 510 -830 0 1 {name=p3 lab=ZZ5} C {lab_pin.sym} 960 -830 0 1 {name=p5 lab=ZZ6} C {lab_wire.sym} 550 -930 0 0 {name=l3 sig_type=std_logic lab=RRSSTT} C {lab_wire.sym} 550 -910 0 0 {name=l4 sig_type=std_logic lab=CCKK} C {lab_wire.sym} 550 -870 0 0 {name=l5 sig_type=std_logic lab=BB} -C {doublepin.sym} 330 -1110 0 0 {name=x3} -C {doublepin.sym} 780 -1110 0 0 {name=x4} -C {lab_pin.sym} 180 -1120 0 0 {name=l6 sig_type=std_logic lab=AA} +C {doublepin.sym} 330 -1110 0 0 {name=x3 +net_name=true} +C {doublepin.sym} 780 -1110 0 0 {name=x4 +net_name=true} +C {lab_pin.sym} 180 -1120 0 0 {name=l6 sig_type=std_logic lab=AA[3:0]} C {lab_pin.sym} 510 -1060 0 1 {name=p1 lab=ZZ3} C {lab_pin.sym} 960 -1060 0 1 {name=p2 lab=ZZ4} C {lab_pin.sym} 180 -1160 0 0 {name=l7 sig_type=std_logic lab=RRSSTT} C {lab_pin.sym} 180 -1140 0 0 {name=l8 sig_type=std_logic lab=CCKK} C {lab_pin.sym} 180 -1100 0 0 {name=l9 sig_type=std_logic lab=BB} -C {lab_pin.sym} 930 -1120 0 1 {name=l10 sig_type=std_logic lab=AA} +C {lab_pin.sym} 930 -1120 0 1 {name=l10 sig_type=std_logic lab=AA[3:0]} C {lab_pin.sym} 930 -1160 0 1 {name=l11 sig_type=std_logic lab=RRSSTT} C {lab_pin.sym} 930 -1140 0 1 {name=l12 sig_type=std_logic lab=CCKK} C {lab_pin.sym} 930 -1100 0 1 {name=l13 sig_type=std_logic lab=BB} -C {doublepin.sym} 330 -1340 0 0 {name=x5} -C {doublepin.sym} 780 -1340 0 0 {name=x6} -C {lab_pin.sym} 180 -1350 0 0 {name=l14 sig_type=std_logic lab=AA} +C {doublepin.sym} 330 -1340 0 0 {name=x5 +net_name=true} +C {doublepin.sym} 780 -1340 0 0 {name=x6 +net_name=true} +C {lab_pin.sym} 180 -1350 0 0 {name=l14 sig_type=std_logic lab=AA[3:0]} C {lab_pin.sym} 510 -1290 0 1 {name=p4 lab=ZZ1} C {lab_pin.sym} 960 -1290 0 1 {name=p6 lab=ZZ2} C {lab_pin.sym} 180 -1390 0 0 {name=l15 sig_type=std_logic lab=RRSSTT} C {lab_pin.sym} 180 -1370 0 0 {name=l16 sig_type=std_logic lab=CCKK} C {lab_pin.sym} 180 -1330 0 0 {name=l17 sig_type=std_logic lab=BB} -C {lab_pin.sym} 930 -1350 0 1 {name=l18 sig_type=std_logic lab=AA} +C {lab_pin.sym} 930 -1350 0 1 {name=l18 sig_type=std_logic lab=AA[3:0]} C {lab_pin.sym} 930 -1390 0 1 {name=l19 sig_type=std_logic lab=RRSSTT} C {lab_pin.sym} 930 -1370 0 1 {name=l20 sig_type=std_logic lab=CCKK} C {lab_pin.sym} 930 -1330 0 1 {name=l21 sig_type=std_logic lab=BB} -C {lab_wire.sym} 550 -1350 0 0 {name=l22 sig_type=std_logic lab=AA} +C {lab_wire.sym} 550 -1350 0 0 {name=l22 sig_type=std_logic lab=AA[3:0]} C {lab_wire.sym} 550 -1390 0 0 {name=l23 sig_type=std_logic lab=RRSSTT} C {lab_wire.sym} 550 -1370 0 0 {name=l24 sig_type=std_logic lab=CCKK} C {lab_wire.sym} 550 -1330 0 0 {name=l25 sig_type=std_logic lab=BB} C {lab_pin.sym} 180 -660 0 0 {name=l33 sig_type=std_logic lab=BB} -C {doublepin.sym} 330 -880 0 0 {name=x1} +C {doublepin.sym} 330 -880 0 0 {name=x1 +net_name=true} C {lab_pin.sym} 510 -620 0 1 {name=p7 lab=ZZ7} C {lab_pin.sym} 630 -620 0 0 {name=p8 lab=ZZ8} -C {lab_pin.sym} 180 -680 0 0 {name=l30 sig_type=std_logic lab=AA} +C {lab_pin.sym} 180 -680 0 0 {name=l30 sig_type=std_logic lab=AA[3:0]} C {lab_pin.sym} 180 -720 0 0 {name=l31 sig_type=std_logic lab=RRSSTT} C {lab_pin.sym} 180 -700 0 0 {name=l32 sig_type=std_logic lab=CCKK} -C {doublepin.sym} 330 -670 0 0 {name=x7} +C {doublepin.sym} 330 -670 0 0 {name=x7 +net_name=true} C {ipin.sym} 100 -80 0 0 { name=p9 lab=RRSSTT } C {ipin.sym} 100 -100 0 0 { name=p10 lab=CCKK } C {ipin.sym} 100 -120 0 0 { name=p11 lab=BB } -C {ipin.sym} 100 -140 0 0 { name=p12 lab=AA } -C {opin.sym} 270 -120 0 0 { name=p13 lab=ZZ[17..1]} +C {ipin.sym} 100 -140 0 0 { name=p12 lab=AA[3:0] } +C {opin.sym} 270 -120 0 0 { name=p13 lab=ZZ[21..1]} C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"} C {lab_pin.sym} 1410 -620 0 1 {name=p8 lab=ZZ9} -C {doublepin.sym} 1230 -460 0 0 {name=x10} -C {doublepin.sym} 810 -460 0 1 {name=x11} +C {doublepin.sym} 1110 -460 0 0 {name=x10 +net_name=true} +C {doublepin.sym} 810 -460 0 1 {name=x11 +net_name=true} C {lab_pin.sym} 510 -410 0 1 {name=p7 lab=ZZ12} C {lab_pin.sym} 630 -410 0 0 {name=p8 lab=ZZ11} -C {doublepin.sym} 330 -460 0 0 {name=x12} -C {lab_pin.sym} 1410 -410 0 1 {name=p1 lab=ZZ10} -C {doublepin.sym} 1370 -1040 0 0 {name=x13} +C {doublepin.sym} 330 -460 0 0 {name=x12 +net_name=true} +C {lab_pin.sym} 1290 -410 0 1 {name=p1 lab=ZZ10} +C {doublepin.sym} 1370 -1040 0 0 {name=x13 +net_name=true} C {lab_pin.sym} 1550 -990 0 1 {name=p2 lab=ZZ13} -C {lab_pin.sym} 1520 -1050 0 1 {name=l10 sig_type=std_logic lab=AA} +C {lab_pin.sym} 1520 -1050 0 1 {name=l1 sig_type=std_logic lab=AA[3:0]} C {lab_pin.sym} 1520 -1090 0 1 {name=l11 sig_type=std_logic lab=RRSSTT} C {lab_pin.sym} 1520 -1070 0 1 {name=l12 sig_type=std_logic lab=CCKK} C {lab_pin.sym} 1520 -1030 0 1 {name=l13 sig_type=std_logic lab=BB} -C {doublepin.sym} 1370 -1300 0 1 {name=x14} +C {doublepin.sym} 1370 -1300 0 1 {name=x14 +net_name=true} C {lab_pin.sym} 1190 -1250 0 0 {name=p2 lab=ZZ14} -C {lab_pin.sym} 1520 -1310 0 1 {name=l10 sig_type=std_logic lab=AA} +C {lab_pin.sym} 1520 -1310 0 1 {name=l3 sig_type=std_logic lab=AA[3:0]} C {lab_pin.sym} 1520 -1350 0 1 {name=l11 sig_type=std_logic lab=RRSSTT} C {lab_pin.sym} 1520 -1330 0 1 {name=l12 sig_type=std_logic lab=CCKK} C {lab_pin.sym} 1520 -1290 0 1 {name=l13 sig_type=std_logic lab=BB} -C {doublepin.sym} 330 -230 0 0 {name=x17} -C {doublepin.sym} 810 -230 0 1 {name=x16} +C {doublepin.sym} 330 -230 0 0 {name=x17[1:0] +net_name=true} +C {doublepin.sym} 810 -230 0 1 {name=x16[1:0] +net_name=true} C {lab_pin.sym} 510 -180 0 1 {name=p7 lab=ZZ17} C {lab_pin.sym} 630 -180 0 0 {name=p8 lab=ZZ16} -C {doublepin.sym} 1230 -230 0 0 {name=x15} +C {doublepin.sym} 1230 -230 0 0 {name=x22[1:0] +net_name=true} C {lab_pin.sym} 1410 -180 0 1 {name=p1 lab=ZZ15} -C {inv_ngspice.sym} 80 -260 0 0 {name=x18 ROUT=1000} +C {inv_ngspice.sym} 80 -260 0 0 {name=x18 ROUT=1000 net_name=true} +C {inv_ngspice.sym} 140 -450 0 0 {name=x19 ROUT=1000 net_name=true} +C {doublepin.sym} 1590 -460 0 0 {name=x20 +net_name=true} +C {lab_pin.sym} 1770 -310 0 1 {name=p8 lab=ZZ18} +C {doublepin.sym} 1890 -460 0 0 {name=x21 +net_name=true} +C {lab_pin.sym} 2070 -310 0 1 {name=p8 lab=ZZ19} +C {inv_ngspice.sym} 720 -350 0 0 {name=x15 ROUT=1000 net_name=true} +C {doublepin.sym} 1410 -870 0 0 {name=x23 +net_name=true} +C {lab_wire.sym} 1180 -880 0 0 {name=l2 sig_type=std_logic lab=AA[3:0]} +C {lab_pin.sym} 1590 -820 0 1 {name=p5 lab=ZZ20} +C {lab_wire.sym} 1180 -920 0 0 {name=l3 sig_type=std_logic lab=RRSSTT} +C {lab_wire.sym} 1180 -900 0 0 {name=l4 sig_type=std_logic lab=CCKK} +C {lab_wire.sym} 1180 -860 0 0 {name=l5 sig_type=std_logic lab=BB} +C {doublepin.sym} 1910 -870 0 1 {name=x24 +net_name=true} +C {lab_pin.sym} 1730 -820 0 0 {name=p5 lab=ZZ21} diff --git a/xschem_library/ngspice/inv_ngspice.sym b/xschem_library/ngspice/inv_ngspice.sym index 3460d3e6..f446b0be 100644 --- a/xschem_library/ngspice/inv_ngspice.sym +++ b/xschem_library/ngspice/inv_ngspice.sym @@ -1,4 +1,5 @@ -v {xschem version=2.9.9 file_version=1.2 } +v {xschem version=3.1.0 file_version=1.2 +} G {} K {type=subcircuit format="@name @pinlist @symname ROUT=@ROUT" @@ -20,3 +21,5 @@ T {@name} 25 -22 0 0 0.2 0.2 {} T {Y} 7.5 -6.5 0 1 0.2 0.2 {} T {A} -17.5 -6.5 0 0 0.2 0.2 {} T {ROUT=@ROUT} -25 -42 0 0 0.2 0.2 {} +T {@#1:net_name} -40 6.25 0 0 0.15 0.15 {layer=15} +T {@#0:net_name} 40 6.25 0 1 0.15 0.15 {layer=15}