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xschem
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speed up draw selection for big datasets, make "drill_hilight" work again after hilight infrastructure changes, fix hilight elements with errors after netlisting, after hilight changes

This commit is contained in:
Stefan Frederik 2020-12-20 19:48:37 +01:00
parent dfa58a0a08
commit 35efb0228a
7 changed files with 52 additions and 30 deletions
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12
src/draw.c
View File

@ -517,6 +517,7 @@ void draw_symbol(int what,int c, int n,int layer,short tmp_flip, short rot,
(xctx->inst[n].y2 - xctx->inst[n].y1) * xctx->mooz < 3) {
drawrect(4, NOW, xctx->inst[n].xx1, xctx->inst[n].yy1, xctx->inst[n].xx2, xctx->inst[n].yy2, 0);
xctx->inst[n].flags|=1;
return;
}
else {
xctx->inst[n].flags&=~1;
@ -681,10 +682,14 @@ void draw_temp_symbol(int what, GC gc, int n,int layer,short tmp_flip, short rot
xctx->inst[n].flags|=1;
return;
}
else if(!only_probes && (xctx->inst[n].x2 - xctx->inst[n].x1) * xctx->mooz < 3 &&
(xctx->inst[n].y2 - xctx->inst[n].y1) * xctx->mooz < 3) {
drawtemprect(gc, what, xctx->inst[n].xx1 + xoffset, xctx->inst[n].yy1 + yoffset,
xctx->inst[n].xx2 + xoffset, xctx->inst[n].yy2 + yoffset);
xctx->inst[n].flags|=1;
return;
}
else xctx->inst[n].flags&=~1;
/* following code handles different text color for labels/pins 06112002 */
} else if(xctx->inst[n].flags&1) {
dbg(2, "draw_symbol(): skipping inst %d\n", n);
return;
@ -706,7 +711,6 @@ void draw_temp_symbol(int what, GC gc, int n,int layer,short tmp_flip, short rot
}
for(j=0;j< symptr->polygons[layer];j++)
{
/*fprintf(errfp, "draw_temp_symbol: polygon\n"); */
polygon = (symptr->poly[layer])[j];
{ /* scope block so we declare some auxiliary arrays for coord transforms. 20171115 */

16
src/hilight.c
View File

@ -851,15 +851,17 @@ void hilight_net(int to_waveform)
switch(xctx->sel_array[i].type)
{
case WIRE:
if(!bus_hilight_lookup(xctx->wire[n].node, xctx->hilight_color, XINSERT)) { /* sets xctx->hilight_nets=1 */
if(to_waveform == GAW) send_net_to_gaw(sim_is_xyce, xctx->wire[n].node);
if(incr_hilight) xctx->hilight_color++;
}
break;
/* sets xctx->hilight_nets=1 */
if(!bus_hilight_lookup(xctx->wire[n].node, xctx->hilight_color, XINSERT)) {
if(to_waveform == GAW) send_net_to_gaw(sim_is_xyce, xctx->wire[n].node);
if(incr_hilight) xctx->hilight_color++;
}
break;
case ELEMENT:
type = (xctx->inst[n].ptr+ xctx->sym)->type;
if( type && xctx->inst[n].node && IS_LABEL_SH_OR_PIN(type) ) { /* instance must have a pin! */
if(!bus_hilight_lookup(xctx->inst[n].node[0], xctx->hilight_color, XINSERT)) { /*sets xctx->hilight_nets=1 */
/* sets xctx->hilight_nets=1 */
if(!bus_hilight_lookup(xctx->inst[n].node[0], xctx->hilight_color, XINSERT)) {
if(to_waveform == GAW) send_net_to_gaw(sim_is_xyce, xctx->inst[n].node[0]);
if(incr_hilight) xctx->hilight_color++;
}
@ -877,12 +879,12 @@ void hilight_net(int to_waveform)
break;
}
}
propagate_hilights(1);
if(!incr_hilight) xctx->hilight_color++;
if(enable_drill) {
drill_hilight();
/*traverse_schematic(); */
}
propagate_hilights(1);
tcleval("if { [info exists gaw_fd] } {close $gaw_fd; unset gaw_fd}\n");
}

10
src/scheduler.c
View File

@ -1675,6 +1675,14 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
if(argc>2) print_spice_element(stderr, atoi(argv[2]));
}
else if(!strcmp(argv[1],"propagate_hilights"))
{
int set = 1;
cmd_found = 1;
if(argc>=3) set = atoi(argv[2]);
propagate_hilights(set);
}
else if(!strcmp(argv[1],"push_undo"))
{
cmd_found = 1;
@ -1691,7 +1699,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
xctx->prep_hash_wires=0;
xctx->prep_net_structs=0;
xctx->prep_hi_structs=0;
prepare_netlist_structs(0);
prepare_netlist_structs(1);
Tcl_ResetResult(interp);
}

13
src/spice_netlist.c
View File

@ -157,9 +157,10 @@ void global_spice_netlist(int global) /* netlister driver */
/* preserve current level instance flags before descending hierarchy for netlisting, restore later */
stored_flags = my_calloc(146, xctx->instances, sizeof(unsigned int));
for(i=0;i<xctx->instances;i++) stored_flags[i] = xctx->inst[i].color;
if(global)
{
{
int saved_hilight_nets = xctx->hilight_nets;
unselect_all();
remove_symbols(); /* 20161205 ensure all unused symbols purged before descending hierarchy */
load_schematic(1, xctx->sch[xctx->currsch], 0);
@ -202,10 +203,12 @@ void global_spice_netlist(int global) /* netlister driver */
prepare_netlist_structs(1); /* so 'lab=...' attributes for unnamed nets are set */
/* symbol vs schematic pin check, we do it here since now we have ALL symbols loaded */
sym_vs_sch_pins();
/* restore hilight flags from errors found analyzing top level before descending hierarchy */
for(i=0;i<xctx->instances; i++) xctx->inst[i].color = stored_flags[i];
draw_hilight_net(1);
if(!xctx->hilight_nets) xctx->hilight_nets = saved_hilight_nets;
}
/* restore hilight flags from errors found analyzing top level before descending hierarchy */
for(i=0;i<xctx->instances; i++) xctx->inst[i].color = stored_flags[i];
propagate_hilights(1);
draw_hilight_net(1);
my_free(945, &stored_flags);
/* print globals nodes found in netlist 28032003 */

10
src/tedax_netlist.c
View File

@ -87,6 +87,7 @@ void global_tedax_netlist(int global) /* netlister driver */
if(global) /* was if(global) ... 20180901 no hierarchical tEDAx netlist for now */
{
int saved_hilight_nets = xctx->hilight_nets;
unselect_all();
remove_symbols(); /* 20161205 ensure all unused symbols purged before descending hierarchy */
load_schematic(1, xctx->sch[xctx->currsch], 0);
@ -115,11 +116,12 @@ void global_tedax_netlist(int global) /* netlister driver */
/* symbol vs schematic pin check, we do it here since now we have ALL symbols loaded */
sym_vs_sch_pins();
/* restore hilight flags from errors found analyzing top level before descending hierarchy */
for(i=0;i<xctx->instances; i++) xctx->inst[i].color = stored_flags[i];
draw_hilight_net(1);
if(!xctx->hilight_nets) xctx->hilight_nets = saved_hilight_nets;
}
/* restore hilight flags from errors found analyzing top level before descending hierarchy */
for(i=0;i<xctx->instances; i++) xctx->inst[i].color = stored_flags[i];
propagate_hilights(1);
draw_hilight_net(1);
my_free(965, &stored_flags);
/* print globals nodes found in netlist 28032003 */

11
src/verilog_netlist.c
View File

@ -275,6 +275,7 @@ void global_verilog_netlist(int global) /* netlister driver */
if(global)
{
int saved_hilight_nets = xctx->hilight_nets;
unselect_all();
remove_symbols(); /* 20161205 ensure all unused symbols purged before descending hierarchy */
@ -316,12 +317,12 @@ void global_verilog_netlist(int global) /* netlister driver */
prepare_netlist_structs(1); /* so 'lab=...' attributes for unnamed nets are set */
/* symbol vs schematic pin check, we do it here since now we have ALL symbols loaded */
sym_vs_sch_pins();
/* restore hilight flags from errors found analyzing top level before descending hierarchy */
for(i=0;i<xctx->instances; i++) xctx->inst[i].color = stored_flags[i];
draw_hilight_net(1);
if(!xctx->hilight_nets) xctx->hilight_nets = saved_hilight_nets;
}
/* restore hilight flags from errors found analyzing top level before descending hierarchy */
for(i=0;i<xctx->instances; i++) xctx->inst[i].color = stored_flags[i];
propagate_hilights(1);
draw_hilight_net(1);
my_free(1074, &stored_flags);
dbg(1, "global_verilog_netlist(): starting awk on netlist!\n");

10
src/vhdl_netlist.c
View File

@ -328,6 +328,7 @@ void global_vhdl_netlist(int global) /* netlister driver */
if(global)
{
int saved_hilight_nets = xctx->hilight_nets;
unselect_all();
remove_symbols(); /* 20161205 ensure all unused symbols purged before descending hierarchy */
load_schematic(1, xctx->sch[xctx->currsch], 0);
@ -370,11 +371,12 @@ void global_vhdl_netlist(int global) /* netlister driver */
/* symbol vs schematic pin check, we do it here since now we have ALL symbols loaded */
sym_vs_sch_pins();
/* restore hilight flags from errors found analyzing top level before descending hierarchy */
for(i=0;i<xctx->instances; i++) xctx->inst[i].color = stored_flags[i];
draw_hilight_net(1);
if(!xctx->hilight_nets) xctx->hilight_nets = saved_hilight_nets;
}
/* restore hilight flags from errors found analyzing top level before descending hierarchy */
for(i=0;i<xctx->instances; i++) xctx->inst[i].color = stored_flags[i];
propagate_hilights(1);
draw_hilight_net(1);
my_free(1088, &stored_flags);
dbg(1, "global_vhdl_netlist(): starting awk on netlist!\n");
if(!split_files) {