diff --git a/src/draw.c b/src/draw.c
index 8e929657..39da9821 100644
--- a/src/draw.c
+++ b/src/draw.c
@@ -517,6 +517,7 @@ void draw_symbol(int what,int c, int n,int layer,short tmp_flip, short rot,
                        (xctx->inst[n].y2 - xctx->inst[n].y1) * xctx->mooz < 3) {
       drawrect(4, NOW, xctx->inst[n].xx1, xctx->inst[n].yy1, xctx->inst[n].xx2, xctx->inst[n].yy2, 0);
       xctx->inst[n].flags|=1;
+      return;
     }
     else {
       xctx->inst[n].flags&=~1;
@@ -681,10 +682,14 @@ void draw_temp_symbol(int what, GC gc, int n,int layer,short tmp_flip, short rot
     xctx->inst[n].flags|=1;
     return;
    }
+   else if(!only_probes && (xctx->inst[n].x2 - xctx->inst[n].x1) * xctx->mooz < 3 &&
+                      (xctx->inst[n].y2 - xctx->inst[n].y1) * xctx->mooz < 3) {
+     drawtemprect(gc, what, xctx->inst[n].xx1 + xoffset, xctx->inst[n].yy1 + yoffset, 
+                            xctx->inst[n].xx2 + xoffset, xctx->inst[n].yy2 + yoffset);
+     xctx->inst[n].flags|=1;
+     return;
+   }
    else xctx->inst[n].flags&=~1;
-
-   /* following code handles different text color for labels/pins 06112002 */
-
  } else if(xctx->inst[n].flags&1) {
    dbg(2, "draw_symbol(): skipping inst %d\n", n);
    return;
@@ -706,7 +711,6 @@ void draw_temp_symbol(int what, GC gc, int n,int layer,short tmp_flip, short rot
  }
  for(j=0;j< symptr->polygons[layer];j++)
  {
-   /*fprintf(errfp, "draw_temp_symbol: polygon\n"); */
    polygon = (symptr->poly[layer])[j];
 
    {   /* scope block so we declare some auxiliary arrays for coord transforms. 20171115 */
diff --git a/src/hilight.c b/src/hilight.c
index 5eb1b2ea..4c5aaf66 100644
--- a/src/hilight.c
+++ b/src/hilight.c
@@ -851,15 +851,17 @@ void hilight_net(int to_waveform)
    switch(xctx->sel_array[i].type)
    {
     case WIRE:
-      if(!bus_hilight_lookup(xctx->wire[n].node, xctx->hilight_color, XINSERT)) { /* sets xctx->hilight_nets=1 */
-        if(to_waveform == GAW) send_net_to_gaw(sim_is_xyce, xctx->wire[n].node);
-        if(incr_hilight) xctx->hilight_color++;
-      }
-      break;
+         /* sets xctx->hilight_nets=1 */
+     if(!bus_hilight_lookup(xctx->wire[n].node, xctx->hilight_color, XINSERT)) {
+       if(to_waveform == GAW) send_net_to_gaw(sim_is_xyce, xctx->wire[n].node);
+       if(incr_hilight) xctx->hilight_color++;
+     }
+     break;
     case ELEMENT:
      type = (xctx->inst[n].ptr+ xctx->sym)->type;
      if( type && xctx->inst[n].node && IS_LABEL_SH_OR_PIN(type) ) { /* instance must have a pin! */
-       if(!bus_hilight_lookup(xctx->inst[n].node[0], xctx->hilight_color, XINSERT)) { /*sets xctx->hilight_nets=1 */
+           /* sets xctx->hilight_nets=1 */
+       if(!bus_hilight_lookup(xctx->inst[n].node[0], xctx->hilight_color, XINSERT)) {
          if(to_waveform == GAW) send_net_to_gaw(sim_is_xyce, xctx->inst[n].node[0]);
          if(incr_hilight) xctx->hilight_color++;
        }
@@ -877,12 +879,12 @@ void hilight_net(int to_waveform)
      break;
    }
   }
-  propagate_hilights(1);
   if(!incr_hilight) xctx->hilight_color++;
   if(enable_drill) {
     drill_hilight();
     /*traverse_schematic(); */
   }
+  propagate_hilights(1);
   tcleval("if { [info exists gaw_fd] } {close $gaw_fd; unset gaw_fd}\n");
 }
 
diff --git a/src/scheduler.c b/src/scheduler.c
index d05a475b..f18a993f 100644
--- a/src/scheduler.c
+++ b/src/scheduler.c
@@ -1675,6 +1675,14 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
       if(argc>2) print_spice_element(stderr, atoi(argv[2]));
     }
    
+    else if(!strcmp(argv[1],"propagate_hilights"))
+    {
+      int set = 1;
+      cmd_found = 1;
+      if(argc>=3) set = atoi(argv[2]);
+      propagate_hilights(set);
+    }
+
     else if(!strcmp(argv[1],"push_undo"))
     {
       cmd_found = 1;
@@ -1691,7 +1699,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
       xctx->prep_hash_wires=0;
       xctx->prep_net_structs=0;
       xctx->prep_hi_structs=0;
-      prepare_netlist_structs(0);
+      prepare_netlist_structs(1);
       Tcl_ResetResult(interp);
     }
    
diff --git a/src/spice_netlist.c b/src/spice_netlist.c
index 0f7794e2..b04e81c1 100644
--- a/src/spice_netlist.c
+++ b/src/spice_netlist.c
@@ -157,9 +157,10 @@ void global_spice_netlist(int global)  /* netlister driver */
  /* preserve current level instance flags before descending hierarchy for netlisting, restore later */
  stored_flags = my_calloc(146, xctx->instances, sizeof(unsigned int));
  for(i=0;i<xctx->instances;i++) stored_flags[i] = xctx->inst[i].color;
-
+ 
  if(global)
- {
+ { 
+   int saved_hilight_nets = xctx->hilight_nets;
    unselect_all();
    remove_symbols(); /* 20161205 ensure all unused symbols purged before descending hierarchy */
    load_schematic(1, xctx->sch[xctx->currsch], 0);
@@ -202,10 +203,12 @@ void global_spice_netlist(int global)  /* netlister driver */
    prepare_netlist_structs(1); /* so 'lab=...' attributes for unnamed nets are set */
    /* symbol vs schematic pin check, we do it here since now we have ALL symbols loaded */
    sym_vs_sch_pins();
-   /* restore hilight flags from errors found analyzing top level before descending hierarchy */
-   for(i=0;i<xctx->instances; i++) xctx->inst[i].color = stored_flags[i];
-   draw_hilight_net(1);
+   if(!xctx->hilight_nets) xctx->hilight_nets = saved_hilight_nets;
  }
+ /* restore hilight flags from errors found analyzing top level before descending hierarchy */
+ for(i=0;i<xctx->instances; i++) xctx->inst[i].color = stored_flags[i];
+ propagate_hilights(1);
+ draw_hilight_net(1);
  my_free(945, &stored_flags);
 
  /* print globals nodes found in netlist 28032003 */
diff --git a/src/tedax_netlist.c b/src/tedax_netlist.c
index d1092843..9c6d1cf3 100644
--- a/src/tedax_netlist.c
+++ b/src/tedax_netlist.c
@@ -87,6 +87,7 @@ void global_tedax_netlist(int global)  /* netlister driver */
 
  if(global) /* was if(global) ... 20180901 no hierarchical tEDAx netlist for now */
  {
+   int saved_hilight_nets = xctx->hilight_nets;
    unselect_all();
    remove_symbols(); /* 20161205 ensure all unused symbols purged before descending hierarchy */
    load_schematic(1, xctx->sch[xctx->currsch], 0);
@@ -115,11 +116,12 @@ void global_tedax_netlist(int global)  /* netlister driver */
 
    /* symbol vs schematic pin check, we do it here since now we have ALL symbols loaded */
    sym_vs_sch_pins();
-
-   /* restore hilight flags from errors found analyzing top level before descending hierarchy */
-   for(i=0;i<xctx->instances; i++) xctx->inst[i].color = stored_flags[i];
-   draw_hilight_net(1);
+   if(!xctx->hilight_nets) xctx->hilight_nets = saved_hilight_nets;
  }
+ /* restore hilight flags from errors found analyzing top level before descending hierarchy */
+ for(i=0;i<xctx->instances; i++) xctx->inst[i].color = stored_flags[i];
+ propagate_hilights(1);
+ draw_hilight_net(1);
  my_free(965, &stored_flags);
 
  /* print globals nodes found in netlist 28032003 */
diff --git a/src/verilog_netlist.c b/src/verilog_netlist.c
index e167183b..34432281 100644
--- a/src/verilog_netlist.c
+++ b/src/verilog_netlist.c
@@ -275,6 +275,7 @@ void global_verilog_netlist(int global)  /* netlister driver */
 
  if(global)
  {
+   int saved_hilight_nets = xctx->hilight_nets;
    unselect_all();
    remove_symbols(); /* 20161205 ensure all unused symbols purged before descending hierarchy */
 
@@ -316,12 +317,12 @@ void global_verilog_netlist(int global)  /* netlister driver */
    prepare_netlist_structs(1); /* so 'lab=...' attributes for unnamed nets are set */
    /* symbol vs schematic pin check, we do it here since now we have ALL symbols loaded */
    sym_vs_sch_pins();
-
-   /* restore hilight flags from errors found analyzing top level before descending hierarchy */
-   for(i=0;i<xctx->instances; i++) xctx->inst[i].color = stored_flags[i];
-
-   draw_hilight_net(1);
+   if(!xctx->hilight_nets) xctx->hilight_nets = saved_hilight_nets;
  }
+ /* restore hilight flags from errors found analyzing top level before descending hierarchy */
+ for(i=0;i<xctx->instances; i++) xctx->inst[i].color = stored_flags[i];
+ propagate_hilights(1);
+ draw_hilight_net(1);
  my_free(1074, &stored_flags);
 
  dbg(1, "global_verilog_netlist(): starting awk on netlist!\n");
diff --git a/src/vhdl_netlist.c b/src/vhdl_netlist.c
index 325413f0..9552066f 100644
--- a/src/vhdl_netlist.c
+++ b/src/vhdl_netlist.c
@@ -328,6 +328,7 @@ void global_vhdl_netlist(int global)  /* netlister driver */
 
  if(global)
  {
+   int saved_hilight_nets = xctx->hilight_nets;
    unselect_all();
    remove_symbols(); /* 20161205 ensure all unused symbols purged before descending hierarchy */
    load_schematic(1, xctx->sch[xctx->currsch], 0);
@@ -370,11 +371,12 @@ void global_vhdl_netlist(int global)  /* netlister driver */
    /* symbol vs schematic pin check, we do it here since now we have ALL symbols loaded */
    sym_vs_sch_pins();
 
-   /* restore hilight flags from errors found analyzing top level before descending hierarchy */
-   for(i=0;i<xctx->instances; i++) xctx->inst[i].color = stored_flags[i];
-
-   draw_hilight_net(1);
+   if(!xctx->hilight_nets) xctx->hilight_nets = saved_hilight_nets;
  }
+ /* restore hilight flags from errors found analyzing top level before descending hierarchy */
+ for(i=0;i<xctx->instances; i++) xctx->inst[i].color = stored_flags[i];
+ propagate_hilights(1);
+ draw_hilight_net(1);
  my_free(1088, &stored_flags);
  dbg(1, "global_vhdl_netlist(): starting awk on netlist!\n");
  if(!split_files) {