luke
/
xschem
mirror of https://github.com/StefanSchippers/xschem.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

spaghetti code removal, more reused code

This commit is contained in:
Stefan Frederik 2020-12-20 15:56:29 +01:00
parent 43f6dc03a4
commit dfa58a0a08
6 changed files with 10 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
src/callback.c
View File

@ -694,26 +694,7 @@ int callback(int event, int mx, int my, KeySym key,
if(key=='V' && state == ShiftMask) /* toggle spice/vhdl netlist */
{
netlist_type++; if(netlist_type==6) netlist_type=1;
if(netlist_type == CAD_VHDL_NETLIST)
{
tclsetvar("netlist_type","vhdl");
}
else if(netlist_type == CAD_SPICE_NETLIST)
{
tclsetvar("netlist_type","spice");
}
else if(netlist_type == CAD_VERILOG_NETLIST)
{
tclsetvar("netlist_type","verilog");
}
else if(netlist_type == CAD_TEDAX_NETLIST)
{
tclsetvar("netlist_type","tedax");
}
else if(netlist_type == CAD_SYMBOL_ATTRS)
{
tclsetvar("netlist_type","symbol");
}
override_netlist_type(-1);
break;
}

7
src/hilight.c
View File

@ -88,7 +88,7 @@ int get_color(int value)
x = value%(n_active_layers);
return active_layer[x];
} else {
return cadlayers > 5 ? 5 : cadlayers -1; /* desperate attempt to return a decent tolor */
return cadlayers > 5 ? 5 : cadlayers -1; /* desperate attempt to return a decent color */
}
}
@ -794,7 +794,7 @@ static void send_current_to_gaw(int simtype, const char *node)
void propagate_hilights(int set)
{
int i, hilight_connected_inst;
int i, hilight_connected_inst, hilights=0;
struct hilight_hashentry *entry;
char *type;
@ -810,6 +810,7 @@ void propagate_hilights(int set)
if( xctx->inst[i].node && xctx->inst[i].node[j]) {
entry=bus_hilight_lookup(xctx->inst[i].node[j], 0, XLOOKUP);
if(entry) {
hilights = 1;
if(set) {
xctx->inst[i].color=get_color(entry->value);
} else {
@ -825,10 +826,12 @@ void propagate_hilights(int set)
}
} else if( type && IS_LABEL_SH_OR_PIN(type) ) {
entry=bus_hilight_lookup( xctx->inst[i].lab, 0, XLOOKUP);
if(entry) hilights = 1;
if(entry && set) xctx->inst[i].color = get_color(entry->value);
else if(!entry && !set) xctx->inst[i].color = 0;
}
}
if(!hilights) xctx->hilight_nets = 0;
}
void hilight_net(int to_waveform)

11
src/netlist.c
View File

@ -631,7 +631,6 @@ void prepare_netlist_structs(int for_netlist)
double rx1,ry1;
struct wireentry *wptr;
struct instpinentry *iptr;
struct hilight_hashentry *entry;
int i,j, rects, generic_rects;
char *dir=NULL;
char *type=NULL;
@ -1043,15 +1042,7 @@ void prepare_netlist_structs(int for_netlist)
my_free(841, &global_node);
dbg(2, "prepare_netlist_structs(): returning\n");
if(xctx->hilight_nets) for(i=0;i<xctx->instances;i++){
/* after an undo/load/hierarchy descend/return
* xctx->inst[i].color is gone, so rebuild it for labels/pins */
char *type = (xctx->inst[i].ptr+ xctx->sym)->type;
if(type && xctx->inst[i].color == 0 && IS_LABEL_SH_OR_PIN(type) ) {
entry=bus_hilight_lookup(xctx->inst[i].lab, 0, XLOOKUP);
if(entry) xctx->inst[i].color = get_color(entry->value);
}
}
propagate_hilights(1);
}
int sym_vs_sch_pins()

6
src/save.c
View File

@ -1028,11 +1028,7 @@ void load_schematic(int load_symbols, const char *filename, int reset_undo) /* 2
} else {
if(loaded_symbol) {
netlist_type = save_netlist_type;
if(netlist_type==CAD_VHDL_NETLIST) tclsetvar("netlist_type","vhdl");
else if(netlist_type==CAD_VERILOG_NETLIST) tclsetvar("netlist_type","verilog");
else if(netlist_type==CAD_TEDAX_NETLIST) tclsetvar("netlist_type","tedax");
else if(netlist_type==CAD_SYMBOL_ATTRS) tclsetvar("netlist_type","symbol");
else tclsetvar("netlist_type","spice");
override_netlist_type(-1);
}
loaded_symbol = 0;
}

6
src/scheduler.c
View File

@ -1495,24 +1495,20 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
cmd_found = 1;
if(!strcmp(argv[2],"vhdl")) {
netlist_type=CAD_VHDL_NETLIST;
tclsetvar("netlist_type",argv[2]);
}
else if(!strcmp(argv[2],"verilog")) {
netlist_type=CAD_VERILOG_NETLIST;
tclsetvar("netlist_type",argv[2]);
}
else if(!strcmp(argv[2],"tedax")) {
netlist_type=CAD_TEDAX_NETLIST;
tclsetvar("netlist_type",argv[2]);
}
else if(!strcmp(argv[2],"symbol")) {
netlist_type=CAD_SYMBOL_ATTRS;
tclsetvar("netlist_type",argv[2]);
}
else if(!strcmp(argv[2],"spice")){
netlist_type=CAD_SPICE_NETLIST;
tclsetvar("netlist_type",argv[2]);
}
override_netlist_type(-1); /* set tcl netlist_type */
}
else if(!strcmp(argv[1],"new_schematic"))

6
src/xinit.c
View File

@ -1311,11 +1311,7 @@ int Tcl_AppInit(Tcl_Interp *inter)
else if(!strcmp(tclgetvar("netlist_type"),"symbol") ) netlist_type=CAD_SYMBOL_ATTRS;
else netlist_type=CAD_SPICE_NETLIST;
} else {
if(netlist_type==CAD_VHDL_NETLIST) tclsetvar("netlist_type","vhdl");
else if(netlist_type==CAD_VERILOG_NETLIST) tclsetvar("netlist_type","verilog");
else if(netlist_type==CAD_TEDAX_NETLIST) tclsetvar("netlist_type","tedax");
else if(netlist_type==CAD_SYMBOL_ATTRS) tclsetvar("netlist_type","symbol");
else tclsetvar("netlist_type","spice");
override_netlist_type(-1); /* set tcl netlist_type */
}
split_files=atoi(tclgetvar("split_files"));