fix unwanted head_undo_ptr change when doing a netlist. Add current backannotation info in capa.sym, ind.sym, isource.sym, isource_table.sym
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c4e9310d45
commit
26fbb82f6b
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@ -3046,6 +3046,8 @@ void pop_undo(int redo, int set_modify_status)
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xctx->head_undo_ptr--;
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xctx->head_undo_ptr--;
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xctx->cur_undo_ptr--;
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xctx->cur_undo_ptr--;
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}
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}
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/* was incremented by a previous push_undo() in netlisting code, so restore */
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if(redo == 4 && xctx->head_undo_ptr == xctx->cur_undo_ptr) xctx->head_undo_ptr--;
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if(xctx->cur_undo_ptr<=0) return; /* check undo tail */
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if(xctx->cur_undo_ptr<=0) return; /* check undo tail */
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xctx->cur_undo_ptr--;
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xctx->cur_undo_ptr--;
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} else { /* redo == 2, get data without changing undo stack */
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} else { /* redo == 2, get data without changing undo stack */
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@ -4806,24 +4806,9 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
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Tcl_ResetResult(interp);
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Tcl_ResetResult(interp);
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}
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}
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else if(argc > 2 && atoi(argv[2]) == 2) {
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else if(argc > 2 && atoi(argv[2]) == 2) {
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copy_hierarchy_data(".drw", ".x1.drw");
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dbg(0, "cur=%d, tail=%d, head=%d\n", xctx->cur_undo_ptr, xctx->tail_undo_ptr, xctx->head_undo_ptr);
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Tcl_ResetResult(interp);
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Tcl_ResetResult(interp);
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}
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}
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else if(argc > 2 && atoi(argv[2]) == 3) {
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Xschem_ctx **save_xctx = get_save_xctx();
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save_xctx[1]->raw = save_xctx[0]->raw;
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Tcl_ResetResult(interp);
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}
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else if(argc > 2 && atoi(argv[2]) == 4) {
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Xschem_ctx **save_xctx = get_save_xctx();
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save_xctx[1]->raw = NULL;
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Tcl_ResetResult(interp);
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}
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else if(argc > 2 && atoi(argv[2]) == 5) {
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Xschem_ctx **save_xctx = get_save_xctx();
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Tcl_SetResult(interp, save_xctx[1]->raw == NULL ? "null" : "not null", TCL_VOLATILE);
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}
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}
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}
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/* text x y rot flip text props size draw
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/* text x y rot flip text props size draw
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@ -3765,6 +3765,8 @@ const char *translate(int inst, const char* s)
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if(vsource) my_snprintf(fqdev, len, "i(%c.%s%s.%s)", prefix, path, instname, dev);
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if(vsource) my_snprintf(fqdev, len, "i(%c.%s%s.%s)", prefix, path, instname, dev);
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else if(prefix == 'd')
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else if(prefix == 'd')
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my_snprintf(fqdev, len, "i(@%c.%s%s.%s[id])", prefix, path, instname, dev);
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my_snprintf(fqdev, len, "i(@%c.%s%s.%s[id])", prefix, path, instname, dev);
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else if(prefix == 'i')
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my_snprintf(fqdev, len, "i(@%c.%s%s.%s[current])", prefix, path, instname, dev);
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else my_snprintf(fqdev, len, "i(@%c.%s%s.%s[i])", prefix, path, instname, dev);
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else my_snprintf(fqdev, len, "i(@%c.%s%s.%s[i])", prefix, path, instname, dev);
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} else {
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} else {
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my_snprintf(fqdev, len, "i(%s%s.%s)", path, instname, dev);
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my_snprintf(fqdev, len, "i(%s%s.%s)", path, instname, dev);
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@ -3886,10 +3888,12 @@ const char *translate(int inst, const char* s)
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if(path[0]) {
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if(path[0]) {
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if(vsource) my_snprintf(fqdev, len, "i(%c.%s%s)", prefix, path, dev);
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if(vsource) my_snprintf(fqdev, len, "i(%c.%s%s)", prefix, path, dev);
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else if(prefix=='d') my_snprintf(fqdev, len, "i(@%c.%s%s[id])", prefix, path, dev);
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else if(prefix=='d') my_snprintf(fqdev, len, "i(@%c.%s%s[id])", prefix, path, dev);
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else if(prefix=='i') my_snprintf(fqdev, len, "i(@%c.%s%s[current])", prefix, path, dev);
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else my_snprintf(fqdev, len, "i(@%c.%s%s[i])", prefix, path, dev);
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else my_snprintf(fqdev, len, "i(@%c.%s%s[i])", prefix, path, dev);
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} else {
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} else {
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if(vsource) my_snprintf(fqdev, len, "i(%s)", dev);
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if(vsource) my_snprintf(fqdev, len, "i(%s)", dev);
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else if(prefix == 'd') my_snprintf(fqdev, len, "i(@%s[id])", dev);
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else if(prefix == 'd') my_snprintf(fqdev, len, "i(@%s[id])", dev);
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else if(prefix == 'i') my_snprintf(fqdev, len, "i(@%s[current])", dev);
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else my_snprintf(fqdev, len, "i(@%s[i])", dev);
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else my_snprintf(fqdev, len, "i(@%s[i])", dev);
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}
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}
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} else {
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} else {
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@ -1,4 +1,4 @@
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v {xschem version=3.4.4 file_version=1.2
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v {xschem version=3.4.5 file_version=1.2
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*
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*
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* This file is part of XSCHEM,
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -52,3 +52,4 @@ T {@value} 15 -6.25 0 0 0.2 0.2 {}
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T {@#0:net_name} 10 -28.75 0 0 0.15 0.15 {layer=15}
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T {@#0:net_name} 10 -28.75 0 0 0.15 0.15 {layer=15}
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T {@#1:net_name} 10 20 0 0 0.15 0.15 {layer=15}
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T {@#1:net_name} 10 20 0 0 0.15 0.15 {layer=15}
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T {m=@m} 15 6.25 0 0 0.2 0.2 {}
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T {m=@m} 15 6.25 0 0 0.2 0.2 {}
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T {@spice_get_current} -2.5 5 0 1 0.2 0.2 {layer=15}
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@ -1,4 +1,4 @@
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v {xschem version=3.4.4 file_version=1.2
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v {xschem version=3.4.5 file_version=1.2
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*
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*
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* This file is part of XSCHEM,
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -50,3 +50,4 @@ T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15}
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T {@name} 15 -18.75 0 0 0.2 0.2 {}
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T {@name} 15 -18.75 0 0 0.2 0.2 {}
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T {@value} 15 -3.75 0 0 0.2 0.2 {}
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T {@value} 15 -3.75 0 0 0.2 0.2 {}
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T {m=@m} 15 11.25 0 0 0.2 0.2 {}
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T {m=@m} 15 11.25 0 0 0.2 0.2 {}
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T {@spice_get_current} -12.5 5 0 1 0.2 0.2 {layer=15}
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@ -1,4 +1,4 @@
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v {xschem version=3.4.4 file_version=1.2
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v {xschem version=3.4.5 file_version=1.2
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*
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*
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* This file is part of XSCHEM,
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -38,3 +38,4 @@ T {@name
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@value} 20 -10 0 0 0.2 0.2 {}
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@value} 20 -10 0 0 0.2 0.2 {}
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T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15}
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T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15}
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T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15}
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T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15}
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T {@spice_get_current} -4.375 15 0 1 0.2 0.2 {layer=15}
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@ -1,4 +1,4 @@
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v {xschem version=3.4.4 file_version=1.2
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v {xschem version=3.4.5 file_version=1.2
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*
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*
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* This file is part of XSCHEM,
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -41,3 +41,4 @@ T {@CTRL
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@TABLE} 20 0 0 0 0.2 0.2 {}
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@TABLE} 20 0 0 0 0.2 0.2 {}
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T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15}
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T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15}
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T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15}
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T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15}
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T {@spice_get_current} -8.75 15 0 1 0.2 0.2 {layer=15}
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@ -98,8 +98,8 @@ jpeg_quality=30
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linewidth_mult=2.0
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linewidth_mult=2.0
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hilight_wave=-1}
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hilight_wave=-1}
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B 2 1260 -390 1680 -220 {flags=graph
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B 2 1260 -390 1680 -220 {flags=graph
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y1 = 0
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y1 = 3.35
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y2 = 6.7
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y2 = 10.05
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divy = 4
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divy = 4
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subdivy=1
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subdivy=1
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x1=5e-10
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x1=5e-10
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@ -148,7 +148,8 @@ digital=0
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ypos1=0.00261891
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ypos1=0.00261891
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ypos2=0.51596
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ypos2=0.51596
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jpeg_quality=30
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jpeg_quality=30
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linewidth_mult=2.0}
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linewidth_mult=2.0
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}
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B 2 1260 -1140 1680 -950 {flags=graph
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B 2 1260 -1140 1680 -950 {flags=graph
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y1 = 0
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y1 = 0
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y2 = 1
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y2 = 1
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@ -206,6 +207,8 @@ T {@value} 985 -286.25 0 1 0.3 0.3 {layer=7 name=C1}
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T {m=@m} 985 -263.75 0 1 0.3 0.3 {layer=7 name=C1}
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T {m=@m} 985 -263.75 0 1 0.3 0.3 {layer=7 name=C1}
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T {Floater text
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T {Floater text
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example} 870 -440 0 0 0.4 0.4 {}
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example} 870 -440 0 0 0.4 0.4 {}
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T {@spice_get_current} 875 -598.75 0 0 0.3 0.3 {layer=7 name=L2}
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T {@spice_get_current} 1015 -268.75 0 0 0.3 0.3 {layer=7 name=C1}
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N 1010 -210 1100 -210 {lab=0}
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N 1010 -210 1100 -210 {lab=0}
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N 1100 -300 1100 -210 {lab=0}
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N 1100 -300 1100 -210 {lab=0}
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N 640 -610 730 -610 {lab=#net1}
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N 640 -610 730 -610 {lab=#net1}
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@ -274,10 +277,12 @@ lab=0}
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C {title.sym} 160 -40 0 0 {name=l1 author="Stefan Schippers" net_name=true}
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C {title.sym} 160 -40 0 0 {name=l1 author="Stefan Schippers" net_name=true}
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C {code_shown.sym} 170 -310 0 0 {name=CONTROL
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C {code_shown.sym} 170 -310 0 0 {name=CONTROL
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value="tcleval(
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value="tcleval(
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.option savecurrents
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.control
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.control
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* example of tcl evaluation of code blocks:
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* example of tcl evaluation of code blocks:
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* current path: $path
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* current path: $path
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* schematic: [xschem get current_name]
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* schematic: [xschem get current_name]
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save all
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tran .05u 1m uic
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tran .05u 1m uic
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write solar_panel.raw
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write solar_panel.raw
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quit 0
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quit 0
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