A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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stefan schippers 26fbb82f6b fix unwanted head_undo_ptr change when doing a netlist. Add current backannotation info in capa.sym, ind.sym, isource.sym, isource_table.sym 2023-11-27 00:01:45 +01:00
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doc allow to load raw files even if netlist type set to `symbol`. Better to_eng function, `xschem raw_query value node {}` returns value at cursor b position 2023-11-26 12:54:37 +01:00
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tests poweramp.sch and mos_power_ampli.sch updates 2023-11-19 12:52:57 +01:00
xschem_library fix unwanted head_undo_ptr change when doing a netlist. Add current backannotation info in capa.sym, ind.sym, isource.sym, isource_table.sym 2023-11-27 00:01:45 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions