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xschem/xschem_library/devices/verilog_preprocessor.sym

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verilog_preprocessor and verilog_timescale now use verilog_format instead of format (which is for spice), corrected verilog_netlist.c; better backslash and quote (") escaping and unescaping when using attribute select combobox; for unquoting use "xschem get_tok tok 2" instead of "xschem get_tok tok 0" + regsub ....(remove backslashes)...
2020-10-10 23:21:23 +02:00
v {xschem version=2.9.8 file_version=1.2}
G {}
K {type=verilog_preprocessor
populating xschem git repo
2020-08-08 15:47:34 +02:00
vhdl_ignore=true
spice_ignore=true
tedax_ignore=true
verilog_preprocessor and verilog_timescale now use verilog_format instead of format (which is for spice), corrected verilog_netlist.c; better backslash and quote (") escaping and unescaping when using attribute select combobox; for unquoting use "xschem get_tok tok 2" instead of "xschem get_tok tok 0" + regsub ....(remove backslashes)...
2020-10-10 23:21:23 +02:00
template="name=s1 string=\\"`include \\\\\\"file\\\\\\"\\""
verilog_format="@string"
populating xschem git repo
2020-08-08 15:47:34 +02:00
}
V {}
S {}
E {}
L 4 0 -10 70 -10 {}
L 4 0 -10 0 10 {}
T {PREPROCESSOR DIRECTIVE} 5 -25 0 0 0.3 0.3 {}
T {@string} 15 -5 0 0 0.3 0.3 {font=monospace}