xschem/xschem_library/devices/assign.sym

v {xschem version=2.9.9 file_version=1.2 }
G {}
K {type=delay
verilog_format="assign #@delay @@d =  @@s ;"
vhdl_format=" @@d <=  @@s after @delay ns;"
format="@name @pinlist 0"
template="name=V1 delay=1"
function0="1"}
V {}
S {}
E {}
L 4 -30 0 30 0 {}
L 4 -10 -5 10 0 {}
L 4 -10 5 10 0 {}
B 5 27.5 -2.5 32.5 2.5 {name=d dir=out verilog_type=wire }
B 5 -32.5 -2.5 -27.5 2.5 {name=s dir=in verilog_type=wire goto=0}
T {@name @delay} -25 -10 0 0 0.1 0.1 {}