24 lines
419 B
Plaintext
24 lines
419 B
Plaintext
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v {xschem version=2.9.7 file_version=1.2}
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G {type=architecture
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spice_ignore=true
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verilog_ignore=true
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tedax_ignore=true
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vhdl_ignore=true
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template=" nothing here, use global schematic properties "}
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V {}
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S {}
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E {}
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L 4 0 -10 355 -10 {}
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T {ARCHITECTURE} 5 -30 0 0 0.3 0.3 {}
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T {SPICE
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=====================
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@schprop
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VERILOG
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=====================
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@schverilogprop
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VHDL
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=====================
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@schvhdlprop} 45 5 0 0 0.3 0.3 {}
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