v {xschem version=2.9.7 file_version=1.2}
G {type=architecture
spice_ignore=true
verilog_ignore=true
tedax_ignore=true
vhdl_ignore=true
template=" nothing here, use global schematic properties "}
V {}
S {}
E {}
L 4 0 -10 355 -10 {}
T {ARCHITECTURE} 5 -30 0 0 0.3 0.3 {}
T {SPICE
=====================
@schprop

VERILOG
=====================
@schverilogprop

VHDL
=====================
@schvhdlprop} 45 5 0 0 0.3 0.3 {}