2024-12-20 02:28:38 +01:00
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v {xschem version=3.4.6 file_version=1.2
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2023-10-09 12:49:11 +02:00
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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2024-11-12 20:23:18 +01:00
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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2023-10-09 12:49:11 +02:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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2023-06-08 01:08:05 +02:00
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}
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2020-10-23 23:17:55 +02:00
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G {}
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K {}
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V {}
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S {}
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E {}
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2024-12-20 02:28:38 +01:00
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B 2 680 -520 1290 -250 {flags=graph
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y1=0
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y2=5
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ypos1=0
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ypos2=2
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divy=5
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subdivy=1
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unity=1
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x1=0
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x2=5e-08
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divx=5
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subdivx=1
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xlabmag=1.0
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ylabmag=1.0
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node="in
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out"
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color="4 7"
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dataset=-1
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unitx=1
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logx=0
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logy=0
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}
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2020-10-23 23:17:55 +02:00
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T {To run this example a 'calc_rc' procedure must be defined.
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2023-06-08 01:08:05 +02:00
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I have embedded below procedure in title instance so
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it will be defined on load/drawing
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2020-10-23 23:17:55 +02:00
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Descend into the symbol ('i' key) and see how it is used in the 'format'
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attribute to calculate "Res" and "Cap" subcircuit parameters from W and L
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instance parameters.
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Tcl scripts can be loaded in xcshemrc by appending a tcl file name to variable
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2024-12-20 02:28:38 +01:00
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'tcl_files'.} 20 -520 2 1 0.5 0.5 {layer=8 }
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2022-08-23 10:44:00 +02:00
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T {proc calc_rc \{ L W \} \{
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if \{[catch \{expr 1200*$L/$W\} res]\} \{set res -1\}
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if \{[catch \{expr 1e-3*$W*$L\} cap]\} \{set cap -1\}
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return "Res=$res Cap=$cap"
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2024-12-20 02:28:38 +01:00
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\} } 10 -500 0 0 0.4 0.4 { font=monospace}
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T {Dynamic calculation of subcircuit parameters} 30 -840 0 0 0.8 0.8 {}
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2023-06-08 01:08:05 +02:00
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T {Title symbol has embedded TCL command
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define calc_rc} 330 -110 0 0 0.4 0.4 { layer=6}
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2020-10-23 23:17:55 +02:00
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N 140 -130 140 -100 { lab=0}
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N 140 -210 160 -210 { lab=IN}
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N 140 -210 140 -190 { lab=IN}
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2023-06-08 01:08:05 +02:00
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C {lab_pin.sym} 680 -170 0 1 {name=p1 lab=OUT}
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C {lab_pin.sym} 380 -170 0 0 {name=p2 lab=IN}
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C {title.sym} 160 -30 0 0 {name=l1 author="tcleval([
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if \{ [info commands calc_rc] eq \{\} \} \{
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puts \{defining calc_rc procedure...\}
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puts \{############\}
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proc calc_rc \{ L W \} \{
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if \{[catch \{expr 1200*$L/$W\} res]\} \{set res -1\}
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if \{[catch \{expr 1e-3*$W*$L\} cap]\} \{set cap -1\}
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2024-12-20 02:28:38 +01:00
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return \\"Res=$res Cap=$cap\\"
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2023-06-08 01:08:05 +02:00
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\}
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puts [info body calc_rc]
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puts \{############\}
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\}
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]Stefan Schippers)"
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}
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2020-10-23 23:17:55 +02:00
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C {vsource.sym} 140 -160 0 0 {name=V1 value="pwl 0 0 10n 0 11n 5"}
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C {lab_pin.sym} 140 -100 0 0 {name=l2 sig_type=std_logic lab=0}
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C {lab_pin.sym} 160 -210 0 1 {name=p3 lab=IN}
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2023-06-08 01:08:05 +02:00
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C {rcline.sym} 530 -170 0 0 {name=x1 L=1e-4 W=0.5e-6
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2020-10-23 23:17:55 +02:00
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}
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2024-12-20 02:28:38 +01:00
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C {code_shown.sym} 830 -190 0 0 {name=STIMULI
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2020-10-23 23:17:55 +02:00
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only_toplevel=false
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value="
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.control
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2024-12-20 02:28:38 +01:00
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save all
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tran 0.1n 50n
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write test_backannotated_subckt.raw
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2020-10-23 23:17:55 +02:00
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.endc
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"}
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2024-12-20 02:28:38 +01:00
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C {launcher.sym} 1050 -230 0 0 {name=h5
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descr="load waves"
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tclcommand="xschem raw_read $netlist_dir/test_backannotated_subckt.raw tran"
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}
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