2020-08-08 15:47:34 +02:00
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<title>COMPONENT PROPERTY SYNTAX</title>
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<!-- slide title -->
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<h1>COMPONENT PROPERTY SYNTAX</h1><br>
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<p>
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Component property strings can be set in the usual way with the <kbd>'q'</kbd> on a selected
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component instance or by menu <kbd>Properties --> Edit</kbd>
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</p>
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2021-10-13 17:33:10 +02:00
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<img src="component_properties.png">
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2020-08-08 15:47:34 +02:00
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<p>
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The dialog box allows to change the property string as well as the symbol reference. The property string
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is essentially a list of <kbd>attribute=value</kbd> items. As with symbol properties if a <kbd>value</kbd>
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has white space it should be double-quoted.
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The following property definitions are identical:
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</p>
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<pre class=code>
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name=mchanged_name model=nmos w=20u l=3u m=10
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</pre><br>
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<pre class=code>
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name="mchanged_name" model="nmos" w="20u" l="3u" m="10"
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</pre><br>
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<p>
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Given the role of the <kbd>"</kbd> character, if quoted values are needed escapes must be used, like in
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the following example where the model name will be with quotes in netlist:
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</p>
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<pre class=code>
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name="mchanged_name" model="\"nmos\"" w="20u" l="3u" m="10"
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</pre>
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<p>or</p>
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<pre class=code>
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name="mchanged_name" model=\"nmos\" w="20u" l="3u" m="10"
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</pre>
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<p>
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the resulting SPICE netlist will be:<br>
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<kbd>mchanged_name DRAIN GATE SOURCE BODY "nmos" w=20u l=3u m=10</kbd>
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</p>
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<p>
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There is no limit on the number of <kbd>attribute=value</kbd> items, each attribute should have a corresponding
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<kbd>@attribute</kbd> in the symbol definition format, but this is not a requirement. There are a number
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of special attributes as we will see later.
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</p>
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<p class="important">
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Important: a <kbd>name=<inst_name></kbd> item is mandatory and must be placed
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in component property string to get a valid netlist, as this is the partname or so-called refdes (reference designator).
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If <kbd><inst_name></kbd> is already used in another component XSCHEM will
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auto-rename it to a unique name preserving the first letter (which ts a device type indicator
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for SPICE like netlists).
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</p>
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<h3>PREDEFINED COMPONENT ATTRIBUTES</h3>
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<ul>
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<li><kbd>name</kbd></li>
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<p> This defines the name of the instance.
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Names are unique, so if for example multiple MOS components are
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placed in the design one should be named <kbd>m1</kbd> and the second <kbd>m2</kbd> or anything
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else, provided the names are different. XSCHEM enforces this,
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unless <kbd>Options -> allow duplicated instance names</kbd> is set. If a name is given that already
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exist in the current schematic it will be renamed. Normally the template string defines a default
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name for a given component, and expecially for SPICE compatibility, the first character must NOT
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be changed. For example, the default name for a MOS transistor is <kbd>m1</kbd>, it can be renamed
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for example to <kbd>mcurr_source</kbd> but not for example to <kbd>dcurr_source</kbd>. XSCHEM
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does not enforce that the first character is preserved, it's up to the designer to keep it
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consistent with the component type.</p>
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<li><kbd>embed</kbd></li>
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<p>
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When the <kbd>embed=true</kbd> is set on a component instance
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the corresponding symbol will be saved into the schematic (.sch) file on the next save operation.
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This allows to distribute schematic files that contain the used symbols so these
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will not depend on external library symbols.
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When this attribute is set on a component instance, all instances in the schematic referring to the same
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symbol will use the embedded symbol definition.
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When descending into an embedded symbol, any changes will be local, meaning that no library symbol
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will be affected. The changes will be saved using the embedded tag (<kbd>[...]</kbd>) into the
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schematic file.
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Removing this attribute will revert to external symbols after saving and reloading the schematic file.
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</p>
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<li><kbd>url</kbd></li>
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<p> This attribute defines a location (web page, file) that can be viewed when hitting the
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<kbd><shift>H</kbd> key (or <kbd><Alt> left mouse buttoni</kbd>) on a selected component.
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This is very useful to link a datasheet to a
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component, for example. The default program used to open the url is <kbd>xdg-open</kbd>.
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this can be changed in the <kbd>~/xschemrc</kbd> configuration file with the <kbd>launcher_default_program</kbd>
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variable.
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<kbd>url</kbd> can be an http link or a local file that has a default association known to xdg-open.</p>
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<li><kbd>program</kbd></li>
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<p> this attribute can be used to specify an application to be used to open the <kbd>url</kbd> link,
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if the default application has to be changed or the file type is unknown.
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for example <kbd>program=evince</kbd> may be given to specify an application for a pdf file
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specified with <kbd>url</kbd></p>
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<li><kbd>tclcommand</kbd></li>
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<p> this can be any tcl statement (or group of statements separated by semicolons) including all xschem-specific
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commands, the statement will be executed when pressing the <kbd><shift>H</kbd> key
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(or <kbd><Alt> left mouse button</kbd>) on the selected instance.
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<br>The <kbd>tclcommand</kbd> and <kbd>url</kbd> properties are mutually exclusive.</p>
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2021-10-13 17:33:10 +02:00
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<img src="component_properties3.png">
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2020-08-08 15:47:34 +02:00
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<li><kbd>only_toplevel</kbd></li>
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<p>this attribute is valid only on <kbd>netlist_commands</kbd> type symbols and specifies that the
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symbol should be netlisted only if it is instantiated in the top-most hierarchy. This is very usefull
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for spice commands. Spice commands are placed in a special <kbd>netlist</kbd> component as we will see
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and are meaningfull only when simulating the block, but should be skipped if the component
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is simulated as part of a bigger system which has its own (at higher hierarchy level)
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<kbd>netlist</kbd>component for Spice commands.</p>
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2021-10-13 17:33:10 +02:00
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<img src="component_properties0.png">
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<li><kbd>lock</kbd></li>
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<p> A <kbd>lock=true</kbd> attribute will make the symbol not editable. the only way to make it editable again is
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to right click on it to bring up the edit attributes dialog box and set to false. This is useful for title
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symbols. </p>
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2023-03-10 04:42:21 +01:00
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<li><kbd>hide</kbd></li>
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<p> A <kbd>hide=true</kbd> attribute will only display the symbol bounding box.</p>
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2020-09-30 00:30:48 +02:00
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<li><kbd>highlight</kbd></li>
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<p>If set to <kbd>true</kbd> the symbol will be highlighted when one of the nets attached to its pins are highlighted.</p>
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<li><kbd>net_name</kbd></li>
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<p>If set to <kbd>true</kbd> the <kbd>#n:net_name</kbd> symbol attributes will display the net names attached to pin terminals.
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the <kbd>n</kbd> is a pin number or name.</p>
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2020-08-08 15:47:34 +02:00
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<li><kbd>place</kbd></li>
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2021-09-19 00:21:20 +02:00
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<p>The <kbd>place=end</kbd> attribute is only valid only for <kbd>netlist_commands</kbd> type symbols, and tells
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XSCHEM that this component must be netlisted last. This is necessary for some spice commands
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that need to be placed <b>after</b> the rest of the netlist.</p>
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2021-09-19 00:21:20 +02:00
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<p>The <kbd>place=header</kbd> attribute is only valid only for <kbd>netlist_commands</kbd> type symbols
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and spice netlisting mode, it tells XSCHEM that this component must be netlisted in the very first
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part of a spice netlist. This is necessary for some spice commands
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that need to be placed <b>before</b> the rest of the netlist.</p>
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2023-06-07 12:05:12 +02:00
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<li id="spice_ignore"><kbd>vhdl_ignore</kbd></li>
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<li><kbd>spice_ignore</kbd></li>
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<li><kbd>verilog_ignore</kbd></li>
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2023-06-07 12:05:12 +02:00
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<li><kbd>tedax_ignore</kbd></li>
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<p >These 4 attributes tell XSCHEM to ignore completely the instance in the respective netlist formats.
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Allowed values for these attributes are <kbd>true</kbd> (or <kbd>open</kbd>), <kbd>false</kbd> and
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<kbd>short</kbd>
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If <kbd>short</kbd> is specified the instance will short together all its pins. For this to work
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only one of the nets connected to the symbol may have a net label attached to it. All other nets will take this name.
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If more labeled nets connect to the shorted symbol a net short error is reported.
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Shorted instances are displayed in the pin color (red) layer. See in below image the upper netname of R1
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is <kbd>VDD</kbd>. </p>
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<img src="component_properties4.png">
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<p> Disabled components (<kbd>spice_ignore=true</kbd> or <kbd>spice_ignore=open</kbd>) are displayed in grey.</p>
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<img src="component_properties5.png">
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<li><kbd>lvs_ignore</kbd></li>
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<p> This attribute works in the same way as above attributes, may take the values
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<kbd>true</kbd> (or <kbd>open</kbd>), <kbd>false</kbd> or <kbd>short</kbd>, and
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will affect the specific instance behaviour in the same way, but only if tcl variable
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<kbd>lvs_ignore</kbd> is set to <kbd>1</kbd>. This can be done in the Simulation menu:
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<kbd>Set 'lvs_ignore' variable</kbd>. If this <kbd>lvs_ignore</kbd> is set on the instance
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it will be shorted / ignored or kept as is depending on its <kbd>lvs_ignore</kbd> attribute
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and will be effective in all netlising formats. This is mostly used to modify the produced netlist
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automatically when doing schematic vs layout (LVS) comparison.</p>
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2023-04-13 02:12:02 +02:00
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2023-06-07 12:05:12 +02:00
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<p> By using the <kbd>*_ignore</kbd> attributes you can modify the circuit depending on the value of a tcl variable:</p>
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<img src="component_properties6.png">
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<p> just set the attribute to something like:</p>
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<pre class="code"> spice_ignore="tcleval([if {$IGNORE == 1} {return {true}} else {return {false}}])" </pre>
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<p> or:</p>
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<pre class="code"> spice_ignore="tcleval([if {$IGNORE == 1} {return {short}} else {return {false}}])" </pre><br>
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2023-04-13 02:12:02 +02:00
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<li><kbd>spice_sym_def</kbd></li>
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<li><kbd>verilog_sym_def</kbd></li>
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<li><kbd>vhdl_sym_def</kbd></li>
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<p> If any of these attributes are present and not empty and the symbol type is set to <kbd>subcircuit</kbd>
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the corresponding netlister will ignore the schematic subcircuit for this specific instance
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and dump into the netlist the content of this attribute.
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This attribute must be paired with a <kbd>schematic=...</kbd> attribute set on the instance that tells
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the subcircuit name to use for this particular instance.
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The typical usage is to include a file, example:<br>
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<pre class="code">
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verilog_sym_def="tcleval(`include \"[abs_sym_path verilog_include_file.v]\")"
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</pre>
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</p>
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<p>
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In this example a <kbd>verilog_include_file.v</kbd> is included using the verilog <kbd>`include</kbd> directive.
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In order to generate a full path for it the <kbd>abs_sym_path</kbd> TCL function is used that searches for this file
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in any of the <kbd>XCHEM_LIBRARY_PATH</kbd> directories. Since TCL is used the attribute is wrappend into a tcleval(...),<br>
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The following will appear in the generated netlist:
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<pre class="code">
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// expanding symbol: verilog_include.sym # of pins=3
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// sym_path: /home/schippes/.xschem/xschem_library/verilog_include.sym
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`include "/home/schippes/.xschem/xschem_library/verilog_include_file.v"
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</pre>
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</p>
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2020-08-08 15:47:34 +02:00
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<li><kbd>sig_type</kbd></li>
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<p> For VHDL type netlist, this tells that the current label names a signal (or constant) of
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type <kbd>sig_type</kbd>. For example a label can be placed with name <kbd>TEST</kbd> and
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<kbd>sig_type=BIT</kbd>. The default type for VHDL if this property is missing is <kbd>std_logic</kbd>.
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The following picture shows the usage of <kbd>sig_type</kbd> and the resulting VHDL netlist.
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This property is applicable only to <kbd>label</kbd> type components: <kbd>ipin.sym</kbd>,
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<kbd>iopin.sym</kbd>, <kbd>opin.sym</kbd>, <kbd>lab_pin.sym</kbd>, <kbd>lab_wire.sym</kbd>.
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</p>
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2021-10-13 17:33:10 +02:00
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<img src="component_properties1.png">
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<li><kbd>verilog_type</kbd></li>
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<p>This is the same as sig_type but for verilog netlisting: can be used to declare a <kbd>wire</kbd>
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or a <kbd>reg</kbd> or any other datatype supported by the verilog language.
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</p>
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<li><kbd>generic_type</kbd></li>
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<p><kbd>generic_type</kbd> defines the type of parameters passed to VHDL components.
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Consider the following examples of placement of <kbd>generic_pin</kbd> components in a
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VHDL design:
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</p>
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2021-10-13 17:33:10 +02:00
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<img src="component_properties2.png">
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<p> As you will see in the <a href="parameters.html">parameters</a> slide, generics (they are just
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parameters passed to components) can be passed also via property strings in addition to using
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<kbd>generic_pin</kbd> components.</p>
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<li><kbd>class</kbd></li>
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<p>The <kbd>class</kbd> attribute is used to declare the class of a VHDL signal, most used classes are
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<kbd>signal</kbd> and <kbd>constant</kbd>. Default if missing is <kbd>signal</kbd>.</p>
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<li><kbd>device_model</kbd></li>
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<p>
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This attribute contains a SPICE .model or .subckt specification (<kbd>device_model=".model D1N4148 D ...."</kbd>)
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that will be printed at end of netlist only once for the specified component (D1N4148 in the example).
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<kbd>device_model</kbd> attributes defined at instance level override the <kbd>device_model</kbd> set
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in the symbol if any.
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</p>
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2023-04-13 00:49:38 +02:00
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<li><kbd>schematic</kbd></li>
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<p>
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This attribute specifies an alternate schematic file to open when descending into the subcircuit.
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This is done only for the specific instance allowing to differentiate implementation ona specific
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instance of a given subcircuit.
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The specified schematic must have the same interface (in/out/inout pins) as the base schematic (that
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is inferred from the symbol name).<br>
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2023-04-13 02:12:02 +02:00
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Example: <kbd>schematic=sky130_tests/inv2.sch</kbd>
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2023-04-13 00:49:38 +02:00
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</p>
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2020-08-08 15:47:34 +02:00
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<li><kbd>pinnumber(name)</kbd></li>
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<p> This will override at instance level the value of attribute <kbd>pinnumber</kbd> of pin <kbd>name</kbd> of the symbol.
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This is mainly used for tedax, where by back annotation a connection to a symbol must be changed.</p>
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<li><kbd>pinnumber(index)</kbd></li>
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<p> This will override at instance level the value of attribute <kbd>pinnumber</kbd> of <kbd>index</kbd>th pin of the symbol.
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This is mainly used for tedax, where by back annotation a connection to a symbol must be changed.
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This notation is faster since xschem does not have to find a pin by string matching.</p>
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</ul><br>
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2021-09-20 01:57:04 +02:00
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<h3>TCL ATTRIBUTE SUBSTITUTION</h3>
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<p>
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Any attribute and symbol text can be embedded in a <kbd>tcleval(....)</kbd> construct, the string inside the
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parentheses will be passed to the tcl interpreter for evaluation. This allows to use any tcl
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variable/command/expression. Example: <br>
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<kbd>value="tcleval([expr {[info exists ::resval] ? $::resval : {100k}}])"</kbd><br>
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this attribute will set <kbd>value</kbd> (example: value of a resistor) to 100k if global tcl variable
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<kbd>resval</kbd> is not set or to the value of <kbd>resval</kbd> if set.
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</p>
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2020-08-08 15:47:34 +02:00
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<!-- end of slide -->
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<div class="filler"></div>
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</div>
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<!-- frame footer -->
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<iframe seamless src="xschem_footer.html" class="footer_iframe" >
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</body>
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</html>
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