2020-08-08 15:47:34 +02:00
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<title>XSCHEM TUTORIAL: Bussed nets - Vectors of instances</title>
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<a href="xschem_man.html" class="home">UP</a>
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<!-- slide title -->
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<h1> TUTORIAL: Use Bus/Vector notation for signal bundles / arrays of instances</h1>
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<p>
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XSCHEM has the ability to use a compact notation to represent signal bundles.
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There is no specific 'bus' entity, in XSCHEM a bus is simply a wire with a label representing a bundle of bits,
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the syntax is explained below.
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Normally a net label assigns a name to a wire, for example 'ENABLE', 'RESET', 'CLK' and so on, however more complex formats are available to describe
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multiple bits.
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</p>
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<ul>
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<li><kbd>AAA,BBB,CCC</kbd>: described a bundle of 3 signals, AAA, BBB, CCC.</li>
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<li><kbd>AAA[3:0]</kbd>: describes the set <kbd>AAA[3],AAA[2],AAA[1],AAA[0]</kbd>. The form <kbd>AAA[3:0]</kbd>
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and <kbd>AAA[3],AAA[2],AAA[1],AAA[0]</kbd> are exactly equivalent.</li>
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<li><kbd>AAA[1:0],BBB[5:4]</kbd>: describes the bundle: <kbd>AAA[1],AAA[0],BBB[5],BBB[4]</kbd>.</li>
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<li><kbd>AAA[6:0:2]</kbd>: describes the bundle <kbd>AAA[6],AAA[4],AAA[2],AAA[0]</kbd>.</li>
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<li><kbd>2*AAA[1:0]</kbd>: describes the bundle <kbd>AAA[1],AAA[0],AAA[1],AAA[0]</kbd>.</li>
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<li><kbd>AAA[1:0]*2</kbd>: describes the bundle <kbd>AAA[1],AAA[1],AAA[0],AAA[0]</kbd>.</li>
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<li><kbd>2*(AAA[1:0],BBB)</kbd>: describes the bundle <kbd>AAA[1],AAA[0],BBB,AAA[1],AAA[0],BBB</kbd>.</li>
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<li><kbd>(AAA[1:0],BBB)*2</kbd>: describes the bundle <kbd>AAA[1],AAA[1],AAA[0],AAA[0],BBB,BBB</kbd>.</li>
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</ul>
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<p>
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All the above notations are perfectly valid label net name attributes.<br>
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In a very similar way multiple instances can be placed in a schematic setting the 'name' attribute to a vector notation.<br>
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For example in picture below <kbd>x22[15:0]</kbd> represents 16 inverters with names <kbd>x22[15],x22[14],...,x22[0]</kbd>.
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</p>
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2021-10-13 17:23:05 +02:00
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<img src="busses0.png" width="640">
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2020-08-08 15:47:34 +02:00
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<br>
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<p>
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Recently a new notation has been added for buses that expands without putting brackets:
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</p>
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<ul>
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<li><kbd>AAA[3..0]</kbd>: describes the set <kbd>AAA3,AAA2,AAA1,AAA0</kbd>. The form <kbd>AAA[3..0]</kbd>
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and <kbd>AAA3,AAA2,AAA1,AAA0</kbd> are exactly equivalent.</li>
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<li><kbd>AAA[1..0],BBB[5..4]</kbd>: describes the bundle: <kbd>AAA1,AAA0,BBB5,BBB4</kbd>.</li>
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<li><kbd>AAA[6..0..2]</kbd>: describes the bundle <kbd>AAA6,AAA4,AAA2,AAA0</kbd>.</li>
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<li><kbd>2*AAA[1..0]</kbd>: describes the bundle <kbd>AAA1,AAA0,AAA1,AAA0</kbd>.</li>
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<li><kbd>AAA[1..0]*2</kbd>: describes the bundle <kbd>AAA1,AAA1,AAA0,AAA0</kbd>.</li>
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<li><kbd>2*(AAA[1..0],BBB)</kbd>: describes the bundle <kbd>AAA1,AAA0,BBB,AAA1,AAA0,BBB</kbd>.</li>
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<li><kbd>(AAA[1..0],BBB)*2</kbd>: describes the bundle <kbd>AAA1,AAA1,AAA0,AAA0,BBB,BBB</kbd>.</li>
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</ul>
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<p>
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In following picture there is a main 72 bit bus (the vertical thick wire) and bus ripper symbols
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(<kbd>devices/bus_connect_nolab.sym</kbd>) are used to take slices of bits from the main bus. Wire labels are used to define bus slices.
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To display thick wires for busses, select all wire segments, then press 'q' and add attribute <kbd>bus=true</kbd>.
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</p>
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2021-10-13 17:23:05 +02:00
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<img src="busses1.png" width="640">
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2020-08-08 15:47:34 +02:00
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<p>
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following picture shows an istantiation of 6 inverters:
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</p>
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2021-10-13 17:23:05 +02:00
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<img src="busses2.png" width="640">
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2020-08-08 15:47:34 +02:00
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<p>
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The generated spice netlist is the following:
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</p>
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<pre class="code">
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...
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xinv5 BB0 AA5 bf
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xinv4 BB1 AA4 bf
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xinv3 BB2 AA3 bf
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xinv2 BB3 AA2 bf
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xinv1 BB4 AA1 bf
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xinv0 BB5 AA0 bf
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...
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</pre><br>
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<p>
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Example of a more complex bus routing. main bus is a bundle of 2 buses: DATA_A[0..15] and DATA_B[0..15]
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</p>
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2021-10-13 17:23:05 +02:00
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<img src="busses3.png" width="640">
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2020-08-08 15:47:34 +02:00
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