2020-08-08 15:47:34 +02:00
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<!DOCTYPE html>
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<html>
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<head>
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<title>DEVELOPER INFO</title>
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<link rel="stylesheet" type="text/css" href="xschem_man.css" />
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</style>
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</head>
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<body>
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<!-- start of slide -->
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<div class="content">
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<!-- navigation buttons -->
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2022-01-31 17:48:02 +01:00
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<a href="graphs.html" class="prev">PREV</a>
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2020-08-08 15:47:34 +02:00
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<!-- slide title -->
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<h1>DEVELOPER INFO</h1><br>
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<h3>GENERAL INFORMATION</h3>
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<p>
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XSCHEM uses layers for its graphics, each layer is a logical entity defining graphic attributes
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like color and fill style. There are very few graphical primitive objects:
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</p>
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<ol>
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<li>Lines</li>
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<li>Rectangles</li>
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<li>Open / close Polygons</li>
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<li> Arcs / Circles</li>
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<li>Text</li>
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</ol>
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<p>
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These primitive objects can be drawn on any layer. XSCHEM number of layers can be defined at compile
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time, however there are some predefiend layers (from 0 to 5) that have specific functions:
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</p>
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<ol start="0">
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<li>Background color</li>
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<li>Wire color (nets)</li>
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<li>Selection color / grid</li>
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<li>Text color</li>
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<li>Symbol drawing color</li>
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<li>Pin color</li>
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<li>General purpose</li>
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<li>General purpose</li>
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<li>General purpose</li>
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</ol>
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<p style="margin-left:30px;">
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....
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</p>
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<ol start="20">
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<li>General purpose</li>
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<li>General purpose</li>
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</ol>
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<p>
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Although any layer can be used for drawing it is strongly advisable to avoid the
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background color and the selection color to avoid confusion.
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Drawing begins by painting the background (layer 0), then drawing the grid (layer 1)
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then drawing wires (nets) on layer 2, then all graphical objects (lines, rectangles, polygons)
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starting form layer 0 to the last defined layer.
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</p>
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<h3>SYMBOLS</h3>
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<p>
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There is a primitive object called symbol. Symbols are just a group of primitive graphic objects
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(lines, polygons, rectangles, text) that can be shown as a single atomic entity.
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Once created a symbol can be placed in a schematic. The instantiation of a symbol is called 'component'.
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</p>
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2021-10-13 17:33:10 +02:00
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<img src="building_symbol_03.png">
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<p>
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The above picture shows a resistor symbol, built drawing some lines on layer 4 (green),
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some pins on layer 5 (red) and some text.
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Symbols once created are stored in libraries (library is just a UNIX directory known to XSCHEM)
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and can be placed like just any other primitive object multiple times in a schematic window
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with different orientations.
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</p>
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2021-10-13 17:33:10 +02:00
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<img src="developer_info_01.png">
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<h3>WIRES</h3>
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<p>
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Another special primitive object in XSCHEM is 'Wire', Graphically it is drawn as a line on layer 1 (wires).
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Wires are drawn only on this layer, they are treated differently by XSCHEM since they carry electrical
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information. Electrical connection between components is done by drawing a connecting wire.
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</p>
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<p class="important">
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Since wires are used to build the circuit connectivity it is best to avoid drawing lines on layer 1
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to avoid confusion, since they would appear like wires, but ignored completely for electrical connectivity.
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</p>
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<h3>PROPERTIES </h3>
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<p>
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All XSCHEM objects (wires, lines, rectangles, polygons, text, symbol instance aka component)
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have a property string attached. Any text can be present in a property string, however
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in most cases the property string is organized as a set of <kbd>key=value</kbd> pairs separated by white space.
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In addition to object properties the schematic or symbol view has global properties attached.
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2020-09-14 10:27:45 +02:00
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There is one global property defined per netlisting mode (currently SPICE, VHDL, Verilog, tEDAx) and one additional global property
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for symbols (containing the netlisting rules usually).
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See the <a href="xschem_properties.html">XSCHEM properties</a> section of the manual for more info.
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</p>
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<h3>COORDINATE SYSTEM</h3>
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<p>
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XSCHEM coordinates are stored as double precision floating point numbers, axis orientation is the same as Xorg
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default coordinate orientation:
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</p>
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2021-10-13 17:33:10 +02:00
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<img src="developer_info_02.png">
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<p>
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When drawing objecs in XSCHEM coordinates are snapped to a multiple of 10.0 coordinate units,
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so all drawn objects are easily aligned.
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The snap level can be changed to any value by the user to allow drawing small objects if desired.
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Grid points are shown at multiples of 20.0 coordinate units, by default.
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</p>
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<h2>XSCHEM FILE FORMAT SPECIFICATION</h2>
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<p>
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XSCHEM schematics and symbols are stored in .sch and .sym files respectively. The two file formats are identical, with the
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exception that symbol (.sym) files usually do not contain wires and component instantiations (although they can).
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</p>
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<p>
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every schematic/symbol object has a corresponding record in the file.
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A single character at the beginning of a line, separated by white space from subsequent fields marks the type of object:
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</p>
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<ul>
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<li><kbd>v</kbd> : XSCHEM Version string
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<li><kbd>S</kbd> : Global property associated to the .sch file for SPICE netlisting</li>
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<li><kbd>V</kbd> : Global property associated to the .sch file for VERILOG netlisting</li>
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<li><kbd>G</kbd> : Global property associated to the .sch file for VHDL netlisting OR
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Global property associated to the .sym file for netlisting (in 1,2 file
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format <kbd>K</kbd> is used, although backward compatibility is guaranteed)</li>
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<li><kbd>E</kbd> : Global property associated to the .sch file for tEDAx netlisting</li>
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<li><kbd>K</kbd> : Global property associated to the .sch/sym file for netlisting.<br>
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For schematic it is used if instantiated as a component (file format 1.2 and newer) </li>
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<li><kbd>L</kbd> : Line </li>
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<li><kbd>B</kbd> : Rectangle </li>
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<li><kbd>P</kbd> : Open / Closed polygon </li>
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<li><kbd>A</kbd> : Arc / Circle </li>
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<li><kbd>T</kbd> : Text </li>
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<li><kbd>N</kbd> : Wire, used to connect together components (only in .sch files) </li>
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<li><kbd>C</kbd> : Component instance in a schematic (only in .sch files) </li>
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<li><kbd>[</kbd> : Start of a symbol embedding, the symbol refers to the immediately preceding component instance.
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This tag must immediately follow a component instance (<kbd>C</kbd>).
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See the example here under. A component symbol is embedded into the schematic file when saving
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if the <kbd>embed=true</kbd> attribute is set on one of the component instances.
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Only one copy of the embedded symbol is saved into the schematic and all components
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referring to this symbol will use the embedded definition.
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When a component has an embedded symbol definition immediately following, a <kbd>embed=true</kbd> is
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added to the component property string if not already present.
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</li><br>
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<pre class="code">
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C {TECHLIB/PCH} 620 -810 0 0 {name=x5 model=PCHLV w=4 l=0.09 m=1 embed=true}
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[
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G {type=pmos
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format="@name @pinlist @model w=@w l=@l m=@m"
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verilog_format="@verilog_gate #(@del ) @name ( @@d , @@s , @@g );"
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template=" name=x1 verilog_gate=pmos del=50,50,50 model=PCH w=0.68 l=0.07 m=1 "
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generic_type="model=string"
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}
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V {}
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S {}
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E {}
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L 4 5 20 20 20 {}
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L 4 20 20 20 30 {}
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L 4 5 -20 20 -20 {}
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L 4 20 -30 20 -20 {}
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L 4 -20 0 -10 0 {}
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L 4 5 -27.5 5 27.5 {11}
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L 4 5 -5 10 0 {}
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L 4 5 5 10 0 {}
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L 4 10 0 20 0 {}
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L 18 -2.5 -15 -2.5 15 {}
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B 5 17.5 27.5 22.5 32.5 {name=d dir=inout}
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B 5 -22.5 -2.5 -17.5 2.5 {name=g dir=in}
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B 5 17.5 -32.5 22.5 -27.5 {name=s dir=inout}
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B 5 17.5 -2.5 22.5 2.5 {name=b dir=in}
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A 4 -6.25 0 3.75 270 360 {}
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T {@w/@l*@m} 7.5 -17.5 0 0 0.2 0.2 {}
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T {@name} 7.5 6.25 0 0 0.2 0.2 {999}
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T {@model} 2.5 -27.5 0 1 0.2 0.2 {layer=8}
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T {D} 25 17.5 0 0 0.15 0.15 {layer=13}
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T {NF=@nf} -5 -15 0 1 0.15 0.15 {}
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]
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</pre><br>
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<li><kbd>]</kbd> : End of an embedded symbol. </li>
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</ul>
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<p>
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the object tag in column 1 is followed by space separated fields that completely define the corresponding object.
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</p>
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<h3>VERSION STRING</h3>
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<p>
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Example: <kbd><br>
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v {xschem version=2.9.7 file_version=1.2}</kbd>
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</p>
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<p>
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Two attributes are defined, the xschem version and the file format version.
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Current file format version is 1.2. This string is guaranteed to be the first one in XSCHEM .sch and .sym files.
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2022-06-23 13:42:56 +02:00
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A comment can be added (by manually editing the xschem schematic or symbol file) as shown below:
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</p>
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<pre class="code">
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v {xschem version=3.1.0 file_version=1.2
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* Copyright 2022 Stefan Frederik Schippers
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* https://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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}
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</pre>
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<h3>GLOBAL SCHEMATIC/SYMBOL PROPERTIES</h3>
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<p>
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Example:<kbd><br>
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G {type=regulator<br>
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format="x@name @pinlist r@symname"<br>
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verilog_format="assign @#2 = @#0 ;"<br>
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tedax_format="footprint @name @footprint<br>
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device @name @symname"<br>
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template="name=U1 footprint=TO220"}</kbd>
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</p>
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<p>
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Global properties define a property string bound to the parent schematic/symbol file,
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there is one global property record per netlisting mode,
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currently SPICE, VHDL, Verilog, tEDAx.<br>
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In addition (only in file_format 1.2 and newer) for schematics and symbols there is a global attribute ('K')
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that defines how to netlist the schematic/symbol if placed as a
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symbol into another parent schematic (should be set in the same way as the 'G' global attribute for symbols
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in pre-1.2 file format).
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Normally only 'G' ('K' in 1.2 file format) type property strings are used for symbols and define attributes
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telling netlisters what to do with the symbol, while global property
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strings in schematic files corresponding to the active netlisting mode of XSCHEM are
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copied verbatim to the netlist.<br>
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the object tag (S, V, G, E, K) is followed by the property string enclosed in curly braces
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(<kbd>{...}</kbd>). This allows strings to contain any white space and newlines.
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Curly braces if present in the string are automatically escaped with the '\' character
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by XSCHEM when saving data.<br>
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Example of the 4 property string records for a schematic file:<kbd><br>
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G {} <br>
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V {assign #1500 LDOUT = LDIN +1;<br>
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} <br>
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E {}<br>
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S {}</kbd><br>
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in this case only the verilog-related global property has some definition. This is Verilog code that is copied into the output netlist.
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</p>
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2022-07-02 10:32:04 +02:00
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<p class="important">
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Attribute strings for all Xschem objects are enclosed in curly braces.
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This allows attributes to span multiple lines.
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This component instance:<br>
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<kbd>C {capa.sym} 890 -160 0 0 {name=C4 m=1 value=10u device="tantalium capacitor"}</kbd><br>
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and this one:<br>
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<kbd>C {capa.sym} 890 -160 0 0 {name=C4<br>
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m=1 value=10u<br>
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device="tantalium capacitor"<br>
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}</kbd><br>
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are perfectly equivalent.
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</p>
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<h3>TEXT OBJECT</h3>
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<p>
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Example: <kbd>T {3 of 4 NANDS of a 74ls00} 500 -580 0 0 0.4 0.4 {font=Monospace layer=4}</kbd><br>
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This line defines a text object, the first field after the type tag is the displayed text,
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followed by X and Y coordinates,rotation, mirror,
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horizontal and vertical text size and finally a property string defining some text attributes.
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<ul>
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<li>The displayed text is enclosed in curly braces (<kbd>{...}</kbd>) to allow white space. Literal curly braces
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must be escaped if present in the saved string. XSCHEM will automatically add the escapes where needed on save.</li>
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<li>X ad Y coordinates are saved and retrieved as double precision floating point numbers.</li>
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<li>Rotation and mirror are integers (range [0:3], [0:1] respectively) that define the orientation
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of text objects. Using rotation and mirror text can be aligned to any corner of its bounding box, so there are 4 different
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alignments for vertical text and 4 different alignments for horizontal text. Below picture shows how text is displayed
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with respect to its anchor point.
|
2021-10-13 17:33:10 +02:00
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<img src="developer_info_03.png"></li>
|
2020-08-08 15:47:34 +02:00
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<li> text X and Y sizes are stored as floating point numbers.</li>
|
2020-10-09 03:04:49 +02:00
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<li> Finally a property string is stored with the same syntax as the displayed text field.
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Currently the following attributes are predefined for text objects:<br><br>
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<ul>
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<li><kbd>font</kbd> Name of font to be used (ex: font=Arial)</li>
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<li><kbd>layer</kbd> Number of layer to use for drawing (as in Xschem Layers menu)</li>
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<li><kbd>hcenter</kbd> If set to <kbd>true</kbd> horizontal center text</li>
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<li><kbd>vcenter</kbd> If set to <kbd>true</kbd> vertical center text</li>
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<li><kbd>weight</kbd> If set to <kbd>bold</kbd> use bold style</li>
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<li><kbd>slant</kbd> If set to <kbd> italic</kbd> or <kbd>oblique</kbd> use that style for text</li>
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</ul>
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</li>
|
2020-08-08 15:47:34 +02:00
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</ul>
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</p>
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<h3>WIRE OBJECT</h3>
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<p>
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Example: <kbd>N 890 -130 890 -110 {lab=ANALOG_GND}</kbd><br>
|
2022-01-13 15:40:20 +01:00
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The net 'N' tag is followed by the end point coordinates x1,y1 - x2,y2.
|
2020-08-08 15:47:34 +02:00
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(stored and read as double precision numbers) and a property string, used in this case to name the net.
|
2022-01-13 15:40:20 +01:00
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In most cases you don't need to specify attributes for nets (one exception is the <kbd>bus</kbd> attribute)
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as the <kbd>lab</kbd> attribute is set by xschem when creating a netlist or more generally when
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building the connectivity.
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This means that almost always nets in a xschem schematic are set as in following example:<br>
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<kbd>N 890 -130 890 -110 {}</kbd><br>
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Xschem schematic files store only geometrical data and attributes of the graphic primitives,
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|
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the connectivity and the logical network is obtained by xschem.
|
2020-08-08 15:47:34 +02:00
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|
</p>
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|
<h3>LINE OBJECT</h3>
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<p>
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Example: <kbd>L 4 -50 20 50 20 {This is a line on layer 4}</kbd><br>
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The line 'L' tag is followed by an integer specifying the graphic layer
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followed by the x1,y1 - x2,y2 coordinates of the line and a property string.
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</p>
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|
<h3>RECTANGLE OBJECT</h3>
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|
<p>
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Example: <kbd>B 5 -62.5 -2.5 -57.5 2.5 {name=IN dir=in pinnumber=1}</kbd><br>
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|
The 'Box' 'B' tag is followed by an integer specifying the graphic layer followed
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|
by the x1,y1 - x2,y2 coordinates of the rectangle
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|
and a final property string. This example defines a symbol pin.
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</p>
|
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|
<h3>OPEN / CLOSED POLYGON OBJECT</h3>
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|
<p>
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|
|
Example: <kbd>P 3 5 2450 -210 2460 -170 2500 -170 2510 -210 2450 -210 {}</kbd><br>
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|
the Polygon 'P' tag is followed by an integer specifying the layer number,
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|
|
followed by the number of points (integer),
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|
the x,y coordinates of the polygon points and the property string (empty in this example).
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|
If the last point is coincident to the first point a closed polygon is drawn.
|
2022-01-13 15:40:20 +01:00
|
|
|
A 'fill=true' arribute may be given to fill a closed polygon, in this case a polygon line looks like:<br>
|
2020-08-08 15:47:34 +02:00
|
|
|
<kbd>P 3 5 2450 -210 2460 -170 2500 -170 2510 -210 2450 -210 {fill=true}</kbd><br>
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|
</p>
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|
<h3>ARC OBJECT</h3>
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|
|
<p>
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|
Example: <kbd>A 3 450 -210 120 45 225 {}</kbd><br>
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|
|
The Arc 'A' tag is followed by an integer specifying the layer number, followed by the arc x, y center coordinates,
|
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|
|
the arc radius, the start angle (measured counterclockwise from the three o'clock direction), the arc sweep angle
|
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|
|
(measured counterclockwise from the start angle) and the property string (empty in this example).
|
|
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|
|
Angles are measured in degrees.<br>
|
2021-10-13 17:33:10 +02:00
|
|
|
<img src="developer_info_07.png">
|
2020-08-08 15:47:34 +02:00
|
|
|
</p>
|
|
|
|
|
<h3>COMPONENT INSTANCE</h3>
|
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|
|
<p>
|
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|
|
Example: <kbd>C {capa.sym} 890 -160 0 0 {name=C4 m=1 value=10u device="tantalium capacitor"}</kbd><br>
|
|
|
|
|
Format: <kbd>C {<symbol reference>} <X coord> <Y coord> <rotation>
|
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|
|
<flip> {<attributes>}</kbd><br>
|
|
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|
|
The component instance tag C is followed by a string specifying <kbd>library/symbol</kbd> or only <kbd>symbol</kbd>
|
|
|
|
|
(see <a href="tutorial_xschem_libraries.html">This tutorial about symbol references</a>)
|
|
|
|
|
followed by the x,y coordinates, rotation (integer range [0:3]),
|
|
|
|
|
mirror (integer range [0:1]), and a property string defining various attributes
|
|
|
|
|
including the mandatory <kbd>name=...</kbd> attribute.<br>
|
|
|
|
|
Orientation and mirror meanings are as follows:<br>
|
2021-10-13 17:33:10 +02:00
|
|
|
<img src="developer_info_04.png">
|
2020-08-08 15:47:34 +02:00
|
|
|
</p>
|
|
|
|
|
<h3>EXAMPLE OF A COMPLETE SYMBOL FILE (7805.sym)</h3><br>
|
|
|
|
|
<pre class="code">
|
|
|
|
|
G {type=regulator
|
|
|
|
|
format="x@name @pinlist r@symname"
|
|
|
|
|
verilog_format="assign @#2 = @#0 ;"
|
|
|
|
|
tedax_format="footprint @name @footprint
|
|
|
|
|
device @name @symname"
|
|
|
|
|
template="name=U1 footprint=TO220"}
|
|
|
|
|
V {}
|
|
|
|
|
S {}
|
|
|
|
|
E {}
|
|
|
|
|
L 4 -60 0 -50 0 {}
|
|
|
|
|
L 4 50 0 60 0 {}
|
|
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|
|
L 4 -50 -20 50 -20 {}
|
|
|
|
|
L 4 50 -20 50 20 {}
|
|
|
|
|
L 4 -50 20 50 20 {}
|
|
|
|
|
L 4 -50 -20 -50 20 {}
|
|
|
|
|
L 4 0 20 0 30 {}
|
|
|
|
|
B 5 -62.5 -2.5 -57.5 2.5 {name=IN dir=in pinnumber=1}
|
|
|
|
|
B 5 -2.5 27.5 2.5 32.5 {name=GND dir=inout pinnumber=2}
|
|
|
|
|
B 5 57.5 -2.5 62.5 2.5 {name=OUT dir=out pinnumber=3}
|
|
|
|
|
T {@name} -17.5 -15 0 0 0.2 0.2 {}
|
|
|
|
|
T {@symname} -17.5 0 0 0 0.2 0.2 {}
|
|
|
|
|
T {@#0:pinnumber} -47.5 -2.5 0 0 0.12 0.12 {}
|
|
|
|
|
T {@#1:pinnumber} -2.5 12.5 0 0 0.12 0.12 {}
|
|
|
|
|
T {@#2:pinnumber} 47.5 -2.5 0 1 0.12 0.12 {}
|
|
|
|
|
</pre>
|
2021-10-13 17:33:10 +02:00
|
|
|
<img src="developer_info_05.png"><br>
|
2020-08-08 15:47:34 +02:00
|
|
|
<br>
|
|
|
|
|
<h3>EXAMPLE OF A COMPLETE SCHEMATIC FILE (pcb_test1.sch)</h3><br>
|
|
|
|
|
<pre class="code">
|
|
|
|
|
G {}
|
|
|
|
|
V {}
|
|
|
|
|
S {}
|
|
|
|
|
E {}
|
|
|
|
|
B 20 270 -550 860 -290 {}
|
|
|
|
|
T {3 of 4 NANDS of a 74ls00} 500 -580 0 0 0.4 0.4 {}
|
|
|
|
|
T {EXPERIMENTAL schematic for generating a tEDAx netlist
|
|
|
|
|
1) set netlist mode to 'tEDAx' (Options menu -> tEDAx netlist)
|
|
|
|
|
2) press 'Netlist' button on the right
|
|
|
|
|
3) resulting netlist is in pcb_test1.tdx } 240 -730 0 0 0.5 0.5 {}
|
|
|
|
|
N 230 -330 300 -330 {lab=INPUT_B}
|
|
|
|
|
N 230 -370 300 -370 {lab=INPUT_A}
|
|
|
|
|
N 680 -420 750 -420 {lab=B}
|
|
|
|
|
N 680 -460 750 -460 {lab=A}
|
|
|
|
|
N 400 -350 440 -350 {lab=B}
|
|
|
|
|
N 850 -440 890 -440 {lab=OUTPUT_Y}
|
|
|
|
|
N 230 -440 300 -440 {lab=INPUT_F}
|
|
|
|
|
N 230 -480 300 -480 {lab=INPUT_E}
|
|
|
|
|
N 400 -460 440 -460 {lab=A}
|
|
|
|
|
N 550 -190 670 -190 {lab=VCCFILT}
|
|
|
|
|
N 590 -130 590 -110 {lab=ANALOG_GND}
|
|
|
|
|
N 790 -190 940 -190 {lab=VCC5}
|
|
|
|
|
N 890 -130 890 -110 {lab=ANALOG_GND}
|
|
|
|
|
N 730 -110 890 -110 {lab=ANALOG_GND}
|
|
|
|
|
N 730 -160 730 -110 {lab=ANALOG_GND}
|
|
|
|
|
N 590 -110 730 -110 {lab=ANALOG_GND}
|
|
|
|
|
N 440 -460 680 -460 {lab=A}
|
|
|
|
|
N 500 -420 680 -420 {lab=B}
|
|
|
|
|
N 500 -420 500 -350 {lab=B}
|
|
|
|
|
N 440 -350 500 -350 {lab=B}
|
|
|
|
|
C {title.sym} 160 -30 0 0 {name=l2 author="Stefan"}
|
|
|
|
|
C {74ls00.sym} 340 -350 0 0 {name=U1:2 risedel=100 falldel=200}
|
|
|
|
|
C {74ls00.sym} 790 -440 0 0 {name=U1:1 risedel=100 falldel=200}
|
|
|
|
|
C {lab_pin.sym} 890 -440 0 1 {name=p0 lab=OUTPUT_Y}
|
|
|
|
|
C {capa.sym} 590 -160 0 0 {name=C0 m=1 value=100u device="electrolitic capacitor"}
|
|
|
|
|
C {74ls00.sym} 340 -460 0 0 {name=U1:4 risedel=100 falldel=200 power=VCC5
|
|
|
|
|
url="http://www.engrcs.com/components/74LS00.pdf".sym}
|
|
|
|
|
C {LM7805.pdf"}
|
|
|
|
|
C {lab_pin.sym} 490 -190 0 0 {name=p20 lab=VCC12}
|
|
|
|
|
C {lab_pin.sym} 940 -190 0 1 {name=p22 lab=VCC5}
|
|
|
|
|
C {lab_pin.sym} 590 -110 0 0 {name=p23 lab=ANALOG_GND}
|
|
|
|
|
C {capa.sym} 890 -160 0 0 {name=C4 m=1 value=10u device="tantalium capacitor"}
|
|
|
|
|
C {res.sym} 520 -190 1 0 {name=R0 m=1 value=4.7 device="carbon resistor"}
|
|
|
|
|
C {lab_wire.sym} 620 -460 0 0 {name=l3 lab=A}
|
|
|
|
|
C {lab_wire.sym} 620 -420 0 0 {name=l0 lab=B}
|
|
|
|
|
C {lab_wire.sym} 650 -190 0 0 {name=l1 lab=VCCFILT}
|
|
|
|
|
C {connector.sym} 230 -370 0 0 {name=CONN1 lab=INPUT_A verilog_type=reg}
|
|
|
|
|
C {connector.sym} 230 -330 0 0 {name=CONN2 lab=INPUT_B verilog_type=reg}
|
|
|
|
|
C {connector.sym} 240 -190 0 0 { name=CONN3 lab=OUTPUT_Y }
|
|
|
|
|
C {connector.sym} 230 -480 0 0 {name=CONN6 lab=INPUT_E verilog_type=reg}
|
|
|
|
|
C {connector.sym} 230 -440 0 0 {name=CONN8 lab=INPUT_F verilog_type=reg}
|
|
|
|
|
C {connector.sym} 240 -160 0 0 { name=CONN9 lab=VCC12 }
|
|
|
|
|
C {connector.sym} 240 -130 0 0 { name=CONN14 lab=ANALOG_GND verilog_type=reg}
|
|
|
|
|
C {connector.sym} 240 -100 0 0 { name=CONN15 lab=GND verilog_type=reg}
|
|
|
|
|
C {code.sym} 1030 -280 0 0 {name=TESTBENCH_CODE only_toplevel=false value="initial begin
|
|
|
|
|
$dumpfile(\\"dumpfile.vcd\\");
|
|
|
|
|
$dumpvars;
|
|
|
|
|
INPUT_E=0;
|
|
|
|
|
INPUT_F=0;
|
|
|
|
|
INPUT_A=0;
|
|
|
|
|
INPUT_B=0;
|
|
|
|
|
ANALOG_GND=0;
|
|
|
|
|
#10000;
|
|
|
|
|
INPUT_A=1;
|
|
|
|
|
INPUT_B=1;
|
|
|
|
|
#10000;
|
|
|
|
|
INPUT_E=1;
|
|
|
|
|
INPUT_F=1;
|
|
|
|
|
#10000;
|
|
|
|
|
INPUT_F=0;
|
|
|
|
|
#10000;
|
|
|
|
|
INPUT_B=0;
|
|
|
|
|
#10000;
|
|
|
|
|
$finish;
|
|
|
|
|
end
|
|
|
|
|
|
|
|
|
|
assign VCC12=1;
|
|
|
|
|
|
|
|
|
|
"}
|
|
|
|
|
C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns" }
|
|
|
|
|
</pre>
|
2021-10-13 17:33:10 +02:00
|
|
|
<img src="developer_info_06.png"><br>
|
2020-08-08 15:47:34 +02:00
|
|
|
<br>
|
|
|
|
|
<!-- end of slide -->
|
|
|
|
|
<div class="filler"></div>
|
|
|
|
|
</div>
|
|
|
|
|
|
|
|
|
|
<!-- frame footer -->
|
|
|
|
|
<iframe seamless src="xschem_footer.html" class="footer_iframe" >
|
|
|
|
|
</body>
|
|
|
|
|
</html>
|
|
|
|
|
|
