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Geza Lore
a37e2ee94b
Extend the decoder-pattern case optimization to selectors that are too
wide for a full 2^width lookup table. A decoder-pattern case (where
every case item assigns constants to a fixed set of LHSs) is lowered to
a new AstMachMasked expression. AstMachMasked is emitted as a run-time
VL_MATCHMASKEd_* function call. It contains a packed constant pool table,
'matchp', which is a list of '(mask, bits)' pairs. At runtime, the index of the
first matching entry is returned, and is used to index a value table. This single
(albeit complicated) expression can replace large if-else trees whole, resulting
in much more compact code with fewer static hard to predict branches. It
is worth about 10% speed and 30% code size in some designs.
Example:
```systemverilog
logic [39:0] sel;
always_comb
casez (sel)
40'b???????????????????????????????????????1: out = 8'h01;
40'b??????????????????????????????????????1?: out = 8'h02;
40'b?????????????????????????????????????1??: out = 8'h03;
default: out = 8'hff;
endcase
```
is compiled to:
```c++
out = TABLE_value[VL_MATCHMASKED_Q(sel, CONST_match)];
```
Where 'CONST_match' contains 4 entries, of a 40-bit mask and 40-bit bit
pattern each, and 'TABLE_value' contains 4 entries of the corresponding
8-bit results. (Entries are aligned to word boundaries to avoid runtime
bit swizzling)
..
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SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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Welcome to Verilator
====================
.. list-table::
* - **Welcome to Verilator, the fastest Verilog/SystemVerilog simulator.**
* Accepts Verilog or SystemVerilog
* Performs lint code-quality checks
* Compiles into multithreaded C++, or SystemC
* Creates JSON to front-end your own tools
- |Logo|
* - |verilator multithreaded performance|
- **Fast**
* Outperforms many closed-source commercial simulators
* Single- and multithreaded output models
* - **Widely Used**
* Wide industry and academic deployment
* Out-of-the-box support from Arm and RISC-V vendor IP
* Over 700 contributors
- |verilator usage|
* - |verilator community|
- **Community Driven & Openly Licensed**
* Guided by the `CHIPS Alliance`_ and `Linux Foundation`_
* Open, and free as in both speech and beer
* More simulation for your verification budget
* - **Commercial Support Available**
* Commercial support contracts
* Design support contracts
* Enhancement contracts
- |verilator support|
What Verilator Does
===================
Verilator is invoked with parameters similar to GCC or Synopsys's VCS. It
"Verilates" the specified Verilog or SystemVerilog code by reading it,
performing lint checks, and optionally inserting assertion checks and
coverage-analysis points. It outputs single- or multithreaded .cpp and .h
files, the "Verilated" code.
Verilator can automatically generate a simulator executable (using
``--binary``), or users can write their own C++/SystemC wrapper to
instantiate the model. The resulting Verilated executable performs the
design simulation. Verilator also supports linking Verilator-generated
libraries, optionally encrypted, into other simulators.
Verilator supports all design constructs, most verification constructs,
intra-assignment delays (e.g, `#10`), and events. Tristate-bus (`z`) and
unknowns (`x`) are handled in limited contexts, in a special manor for
performance. It currently may not be the best choice if you are expecting a
full-featured replacement for a closed-source Verilog simulator, performing
SDF annotation, or mixed-signal simulation. However, if you are looking for
a path to migrate SystemVerilog to C++/SystemC, or want high-speed
simulation, Verilator is the tool for you.
Performance
===========
Verilator does not directly translate Verilog HDL to C++ or SystemC.
Rather, Verilator compiles your code into a much faster optimized and
optionally thread-partitioned model, which is in turn wrapped inside a
C++/SystemC module. The results are a compiled Verilog model that executes
even on a single thread over 10x faster than standalone SystemC, and on a
single thread is about 100 times faster than interpreted Verilog simulators
such as `Icarus Verilog`_. Another 2-10x speedup might be gained from
multithreading (yielding 200-1000x total over interpreted simulators).
Verilator has typically similar or better performance versus closed-source
Verilog simulators (e.g., Aldec Riviera-Pro, Cadence Incisive/NC-Verilog,
Mentor ModelSim/Questa, Synopsys VCS, VTOC, and Pragmatic CVer/CVC). But,
Verilator is open-sourced, so you can spend on computes rather than
licenses. Thus, Verilator gives you the best simulation cycles/dollar.
Installation & Documentation
============================
For more information:
- `Verilator installation and package directory structure
<https://verilator.org/install>`_
- `Verilator manual (HTML) <https://verilator.org/verilator_doc.html>`_, or
`Verilator manual (PDF) <https://verilator.org/verilator_doc.pdf>`_
- `Subscribe to Verilator announcements
<https://github.com/verilator/verilator-announce>`_
- `Verilator forum <https://verilator.org/forum>`_
- `Verilator issues <https://verilator.org/issues>`_
Support
=======
Verilator is a community project, guided by the `CHIPS Alliance`_ under the
`Linux Foundation`_.
We appreciate and welcome your contributions in whatever form; please see
`Contributing to Verilator
<https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst>`_.
Thanks to our `Contributors and Sponsors
<https://verilator.org/guide/latest/contributors.html>`_.
Verilator also supports and encourages commercial support models and
organizations; please see `Verilator Commercial Support
<https://verilator.org/verilator_commercial_support>`_.
Related Projects
================
- `Cocotb <https://www.cocotb.org/>`_ - A coroutine-based cosimulation
library for writing testbenches in Python which officially supports
Verilator.
- `GTKwave <https://gtkwave.sourceforge.net/>`_ - Waveform viewer for
Verilator traces.
- `Icarus Verilog`_ - Icarus is a highly-featured interpreted Verilog
simulator. If Verilator does not support your needs, perhaps Icarus may.
- `Surfer <https://surfer-project.org/>`_ - Web or offline waveform viewer
for Verilator traces.
Open License
============
Verilator is Copyright 2003-2026 by Wilson Snyder. (Report bugs to
`Verilator Issues <https://verilator.org/issues>`_.)
Verilator is free software; you can redistribute it and/or modify it under
the terms of either the GNU Lesser General Public License Version 3 or the
Perl Artistic License Version 2.0. See the documentation for more details.
.. _chips alliance: https://chipsalliance.org
.. _icarus verilog: https://steveicarus.github.io/iverilog
.. _linux foundation: https://www.linuxfoundation.org
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.. |verilator support| image:: https://www.veripool.org/img/verilator_support_400x125-min.png