Version bump

Signed-off-by: Wilson Snyder <[email protected]>

Changes

@@ -2,6 +2,28 @@ Revision history for Verilator
 
 The contributors that suggested a given feature are shown in []. Thanks!
 
+* Verilator 3.920 2018-02-01
+
+**    Moving forward, use the git "stable" branch to track the latest release,
+      and git "v#.###" tags for specific releases.
+
+***   Support 'assume' similar to 'assert', bug1269. [Dan Gisselquist]
+
+****  Fix tracing example file output, bug1268. [Enzo Chi]
+
+****  Fix gate optimization out of memory, add --gate-stmts, bug1260. [Alex Solomatnikov]
+
+****  Fix compile error on public real parameters by suppressing, bug1261. [Alex Solomatnikov]
+
+****  Fix input-only tristate comparisons, bug1267. [Alexis G]
+
+****  Fix missing edge type in xml output, msg2480. [Alexis G]
+
+****  Fix compile error with --public and interface bind, bug1264. [Alexis G]
+
+****  Remove c++filt, bug1265. [Stefan Wallentowitz]
+
+
 * Verilator 3.918 2018-01-02
 
 ***   Workaround GCC/clang bug with huge compile times, bug1248.

bin/verilator

@@ -289,6 +289,7 @@ descriptions in the next sections for more information.
     --getenv <var>              Get environment variable with defaults
     --help                      Display this help
      -I<dir>                    Directory to search for includes
+    --gate-stmts <value>        Tune gate optimizer depth
     --if-depth <value>          Tune IFDEPTH warning
      +incdir+<dir>              Directory to search for includes
     --inhibit-sim               Create function to turn off sim
@@ -750,6 +751,11 @@ them properly, e.g. as -GSTR="\"My String\"" or -GSTR='"My String"'.
 
 =back
 
+=item --gate-stmts I<value>
+
+Rarely needed.  Set the maximum number of statements that may be present in
+an equation for the gate substitution optimization to inline that equation.
+
 =item --gdb
 
 Run Verilator underneath an interactive GDB (or VERILATOR_GDB environment

configure.ac

@@ -6,7 +6,7 @@
 
 #AC_INIT([Verilator],[#.### YYYY-MM-DD])
 #AC_INIT([Verilator],[#.### devel])
-AC_INIT([Verilator],[3.918 2018-01-02])
+AC_INIT([Verilator],[3.920 2018-02-01])
 # When releasing, also update header of Changes file
 # and commit using "devel release" or "Version bump" message
 
@@ -167,9 +167,11 @@ AC_DEFUN([_MY_CXX_CHECK_OPT],
 # Macros work such that first option that passes is the one we take
 # gnu++14 is the newest that Verilator supports
 # std++03 is the oldest that Verilator supports
+_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++17)
 _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++14)
 _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++11)
 _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++03)
+_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++17)
 _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++14)
 _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++11)
 _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++03)
@@ -179,6 +181,7 @@ AC_SUBST(CFG_CXXFLAGS_STD_NEWEST)
 _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=std++03)
 _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=std++11)
 _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=std++14)
+_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=std++17)
 _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=gnu++03)
 _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=gnu++11)
 _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=gnu++14)
@@ -218,6 +221,7 @@ AC_SUBST(CFG_CXXFLAGS_PARSER)
 _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_NO_UNUSED,-faligned-new)
 _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_NO_UNUSED,-fbracket-depth=4096)
 _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_NO_UNUSED,-Qunused-arguments)
+_MY_CXX_CHECK_OPT(CFG_CXXFLAGS_NO_UNUSED,-Wno-bool-operation)
 _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_NO_UNUSED,-Wno-parentheses-equality)
 _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_NO_UNUSED,-Wno-sign-compare)
 _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_NO_UNUSED,-Wno-uninitialized)

examples/tracing_c/sim_main.cpp

@@ -90,6 +90,11 @@ int main(int argc, char** argv, char** env) {
         // Evaluate model
         top->eval();
 
+#if VM_TRACE
+        // Dump trace data for this cycle
+        if (tfp) tfp->dump (main_time);
+#endif
+
         // Read outputs
         VL_PRINTF ("[%" VL_PRI64 "d] clk=%x rstl=%x iquad=%" VL_PRI64 "x"
                    " -> oquad=%" VL_PRI64"x owide=%x_%08x_%08x\n",
@@ -102,7 +107,7 @@ int main(int argc, char** argv, char** env) {
 
     // Close trace if opened
 #if VM_TRACE
-    if (tfp) { tfp->close(); }
+    if (tfp) { tfp->close(); tfp = NULL; }
 #endif
 
     //  Coverage analysis (since test passed)

examples/tracing_sc/sc_main.cpp

@@ -94,10 +94,10 @@ int sc_main(int argc, char* argv[]) {
     const char* flag = Verilated::commandArgsPlusMatch("trace");
     if (flag && 0==strcmp(flag, "+trace")) {
         cout << "Enabling waves into logs/vlt_dump.vcd...\n";
-        VerilatedVcdSc* tfp = new VerilatedVcdSc;
-        top->trace (tfp, 99);
+        tfp = new VerilatedVcdSc;
+        top->trace(tfp, 99);
         mkdir("logs", 0777);
-        tfp->open ("logs/vlt_dump.vcd");
+        tfp->open("logs/vlt_dump.vcd");
     }
 #endif
 
@@ -107,13 +107,15 @@ int sc_main(int argc, char* argv[]) {
         // Flush the wave files each cycle so we can immediately see the output
         // Don't do this in "real" programs, do it in an abort() handler instead
         if (tfp) tfp->flush();
+#endif
+
         // Apply inputs
         if (VL_TIME_Q() > 1 && VL_TIME_Q() < 10) {
             reset_l = !1;       // Assert reset
         } else if (VL_TIME_Q() > 1) {
             reset_l = !0;       // Deassert reset
         }
-#endif
+
         // Simulate 1ns
 #if (SYSTEMC_VERSION>=20070314)
         sc_start(1,SC_NS);
@@ -122,20 +124,23 @@ int sc_main(int argc, char* argv[]) {
 #endif
     }
 
-    //  Close Waves
-#if VM_TRACE
-    if (tfp) tfp->close();
-#endif
-
     // Final model cleanup
     top->final();
 
+    // Close trace if opened
+#if VM_TRACE
+    if (tfp) { tfp->close(); tfp = NULL; }
+#endif
+
     //  Coverage analysis (since test passed)
 #if VM_COVERAGE
     mkdir("logs", 0777);
     VerilatedCov::write("logs/coverage.dat");
 #endif
 
+    // Destroy model
+    delete top; top = NULL;
+
     // Fin
     return 0;
 }

src/V3CCtors.cpp

@@ -149,7 +149,9 @@ void V3CCtors::cctorsAll() {
             V3CCtorsVisitor var_reset (modp, "_ctor_var_reset");
             for (AstNode* np = modp->stmtsp(); np; np = np->nextp()) {
                 if (AstVar* varp = np->castVar()) {
-                    var_reset.add(new AstCReset(varp->fileline(), new AstVarRef(varp->fileline(), varp, true)));
+                    if (!varp->isIfaceParent() && !varp->isIfaceRef()) {
+                        var_reset.add(new AstCReset(varp->fileline(), new AstVarRef(varp->fileline(), varp, true)));
+                    }
                 }
             }
         }

src/V3EmitC.cpp

@@ -859,7 +859,7 @@ class EmitCImp : EmitCStmts {
 
     //---------------------------------------
     // VISITORS
-    using EmitCStmts::visit;  // Suppress hidden overloaded virtual function warnng
+    using EmitCStmts::visit;  // Suppress hidden overloaded virtual function warning
     virtual void visit(AstCFunc* nodep) {
 	// TRACE_* and DPI handled elsewhere
 	if (nodep->funcType().isTrace()) return;
@@ -2040,6 +2040,8 @@ void EmitCImp::emitInt(AstNodeModule* modp) {
 		    putsDecoration("// enum WData "+varp->name()+"  //wide");
 		} else if (!varp->valuep()->castConst()) {   // Unsupported for output
 		    //putsDecoration("// enum ..... "+varp->name()+"  //not simple value, see variable above instead");
+                } else if (varp->dtypep()->castBasicDType()
+                           && varp->dtypep()->castBasicDType()->isOpaque()) {  // Can't put out e.g. doubles
 		} else {
 		    puts("enum ");
 		    puts(varp->isQuad()?"_QData":"_IData");
@@ -2077,10 +2079,10 @@ void EmitCImp::emitInt(AstNodeModule* modp) {
     }
     if (v3Global.opt.trace()) {
 	if (modp->isTop()) puts("/// Trace signals in the model; called by application code\n");
-	puts("void trace (VerilatedVcdC* tfp, int levels, int options=0);\n");
+        puts("void trace(VerilatedVcdC* tfp, int levels, int options=0);\n");
 	if (modp->isTop() && optSystemC()) {
 	    puts("/// SC tracing; avoid overloaded virtual function lint warning\n");
-	    puts("virtual void trace (sc_trace_file* tfp) const { ::sc_core::sc_module::trace(tfp); }\n");
+            puts("virtual void trace(sc_trace_file* tfp) const { ::sc_core::sc_module::trace(tfp); }\n");
 	}
     }
 
@@ -2112,9 +2114,9 @@ void EmitCImp::emitInt(AstNodeModule* modp) {
 
     if (v3Global.opt.trace()) {
 	ofp()->putsPrivate(false);  // public:
-	puts("static void traceInit ("+v3Global.opt.traceClassBase()+"* vcdp, void* userthis, uint32_t code);\n");
-	puts("static void traceFull ("+v3Global.opt.traceClassBase()+"* vcdp, void* userthis, uint32_t code);\n");
-	puts("static void traceChg  ("+v3Global.opt.traceClassBase()+"* vcdp, void* userthis, uint32_t code);\n");
+        puts("static void traceInit("+v3Global.opt.traceClassBase()+"* vcdp, void* userthis, uint32_t code);\n");
+        puts("static void traceFull("+v3Global.opt.traceClassBase()+"* vcdp, void* userthis, uint32_t code);\n");
+        puts("static void traceChg("+v3Global.opt.traceClassBase()+"* vcdp, void* userthis, uint32_t code);\n");
     }
     if (v3Global.opt.savable()) {
 	ofp()->putsPrivate(false);  // public:
@@ -2275,9 +2277,9 @@ class EmitCTrace : EmitCStmts {
     void emitTraceSlow() {
 	puts("\n//======================\n\n");
 
-	puts("void "+topClassName()+"::trace (");
+        puts("void "+topClassName()+"::trace(");
 	puts("VerilatedVcdC* tfp, int, int) {\n");
-	puts(  "tfp->spTrace()->addCallback ("
+        puts(  "tfp->spTrace()->addCallback("
 	       "&"+topClassName()+"::traceInit"
 	       +", &"+topClassName()+"::traceFull"
 	       +", &"+topClassName()+"::traceChg, this);\n");
@@ -2292,7 +2294,7 @@ class EmitCTrace : EmitCStmts {
 	puts("if (!Verilated::calcUnusedSigs()) VL_FATAL_MT(__FILE__,__LINE__,__FILE__,\"Turning on wave traces requires Verilated::traceEverOn(true) call before time 0.\");\n");
 
 	puts("vcdp->scopeEscape(' ');\n");
-	puts("t->traceInitThis (vlSymsp, vcdp, code);\n");
+        puts("t->traceInitThis(vlSymsp, vcdp, code);\n");
 	puts("vcdp->scopeEscape('.');\n");  // Restore so later traced files won't break
 	puts("}\n");
 	splitSizeInc(10);
@@ -2302,7 +2304,7 @@ class EmitCTrace : EmitCStmts {
 	putsDecoration("// Callback from vcd->dump()\n");
 	puts(topClassName()+"* t=("+topClassName()+"*)userthis;\n");
 	puts(EmitCBaseVisitor::symClassVar()+" = t->__VlSymsp;  // Setup global symbol table\n");
-	puts("t->traceFullThis (vlSymsp, vcdp, code);\n");
+        puts("t->traceFullThis(vlSymsp, vcdp, code);\n");
 	puts("}\n");
 	splitSizeInc(10);
 
@@ -2318,7 +2320,7 @@ class EmitCTrace : EmitCStmts {
 	puts(topClassName()+"* t=("+topClassName()+"*)userthis;\n");
 	puts(EmitCBaseVisitor::symClassVar()+" = t->__VlSymsp;  // Setup global symbol table\n");
 	puts("if (vlSymsp->getClearActivity()) {\n");
-	puts("t->traceChgThis (vlSymsp, vcdp, code);\n");
+        puts("t->traceChgThis(vlSymsp, vcdp, code);\n");
 	puts("}\n");
 	puts("}\n");
 	splitSizeInc(10);

src/V3EmitMk.cpp

@@ -211,7 +211,7 @@ public:
 
 	    of.puts("\n### Link rules... (from --exe)\n");
 	    of.puts(v3Global.opt.exeName()+": $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a\n");
-	    of.puts("\t$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) $(SC_LIBS) 2>&1 | c++filt\n");
+	    of.puts("\t$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) $(SC_LIBS)\n");
 	    of.puts("\n");
 	}
 

src/V3EmitXml.cpp

@@ -97,6 +97,15 @@ class EmitXmlFileVisitor : public AstNVisitor {
     }
 
     // VISITORS
+    virtual void visit(AstAssignW* nodep) {
+        outputTag(nodep, "contassign"); // IEEE: vpiContAssign
+        outputChildrenEnd(nodep, "contassign");
+    }
+    virtual void visit(AstCell* nodep) {
+        outputTag(nodep, "instance");   // IEEE: vpiInstance
+        puts(" defName="); putsQuoted(nodep->modName());  // IEEE vpiDefName
+        outputChildrenEnd(nodep, "instance");
+    }
     virtual void visit(AstNetlist* nodep) {
 	puts("<netlist>\n");
 	nodep->iterateChildren(*this);
@@ -108,11 +117,6 @@ class EmitXmlFileVisitor : public AstNVisitor {
 	    puts(" topModule=\"1\"");  // IEEE vpiTopModule
 	outputChildrenEnd(nodep, "");
     }
-    virtual void visit(AstCell* nodep) {
-	outputTag(nodep, "instance");	// IEEE: vpiInstance
-	puts(" defName="); putsQuoted(nodep->modName());  // IEEE vpiDefName
-	outputChildrenEnd(nodep, "instance");
-    }
     virtual void visit(AstPin* nodep) {
 	// What we call a pin in verilator is a port in the IEEE spec.
 	outputTag(nodep, "port");	// IEEE: vpiPort
@@ -125,9 +129,10 @@ class EmitXmlFileVisitor : public AstNVisitor {
 	// Children includes vpiHighConn and vpiLowConn; we don't support port bits (yet?)
 	outputChildrenEnd(nodep, "port");
     }
-    virtual void visit(AstAssignW* nodep) {
-	outputTag(nodep, "contassign");	// IEEE: vpiContAssign
-	outputChildrenEnd(nodep, "contassign");
+    virtual void visit(AstSenItem* nodep) {
+        outputTag(nodep, "");
+        puts(" edgeType=\""+cvtToStr(nodep->edgeType().ascii())+"\"");  // IEEE vpiTopModule
+        outputChildrenEnd(nodep, "");
     }
 
     // Data types
@@ -165,7 +170,7 @@ void V3EmitXml::emitxml() {
     of.puts("<!-- DESCR" "IPTION: Verilator output: XML representation of netlist -->\n");
     of.puts("<verilator_xml>\n");
     {
-	stringstream sstr;
+	std::stringstream sstr;
 	FileLine::fileNameNumMapDumpXml(sstr);
 	of.puts(sstr.str());
     }

src/V3Gate.cpp

@@ -195,6 +195,7 @@ private:
     bool		m_buffersOnly;	// Set when we only allow simple buffering, no equations (for clocks)
     AstNodeVarRef*	m_lhsVarRef;	// VarRef on lhs of assignment (what we're replacing)
     bool		m_dedupe;	// Set when we use isGateDedupable instead of isGateOptimizable
+    int                 m_ops;  // Operation count
 
     // METHODS
     void clearSimple(const char* because) {
@@ -205,6 +206,7 @@ private:
     }
     // VISITORS
     virtual void visit(AstNodeVarRef* nodep) {
+        ++m_ops;
 	nodep->iterateChildren(*this);
 	// We only allow a LHS ref for the var being set, and a RHS ref for something else being read.
 	if (nodep->varScopep()->varp()->isSc()) {
@@ -254,6 +256,9 @@ private:
     virtual void visit(AstNode* nodep) {
 	// *** Special iterator
 	if (!m_isSimple) return;	// Fastpath
+        if (++m_ops > v3Global.opt.gateStmts()) {
+            clearSimple("--gate-stmts exceeded");
+        }
 	if (!(m_dedupe ? nodep->isGateDedupable() : nodep->isGateOptimizable())
 	    || !nodep->isPure()
 	    || nodep->isBrancher()) {
@@ -270,6 +275,7 @@ public:
 	m_buffersOnly = buffersOnly;
 	m_lhsVarRef = NULL;
 	m_dedupe = dedupe;
+        m_ops = 0;
 	// Iterate
 	nodep->accept(*this);
 	// Check results
@@ -327,7 +333,7 @@ private:
     // METHODS
     void iterateNewStmt(AstNode* nodep, const char* nonReducibleReason, const char* consumeReason) {
 	if (m_scopep) {
-	    UINFO(4,"   STMT "<<nodep<<endl);
+            UINFO(5,"   STMT "<<nodep<<endl);
 	    // m_activep is null under AstCFunc's, that's ok.
 	    m_logicVertexp = new GateLogicVertex(&m_graph, m_scopep, nodep, m_activep, m_inSlow);
 	    if (nonReducibleReason) {

src/V3Options.cpp

@@ -787,6 +787,10 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
 	    else if ( !strncmp (sw, "-G", strlen("-G"))) {
 		addParameter(string (sw+strlen("-G")), false);
 	    }
+            else if ( !strcmp (sw, "-gate-stmts") && (i+1)<argc ) {
+                shift;
+                m_gateStmts = atoi(argv[i]);
+            }
 	    else if ( !strcmp (sw, "-getenv") && (i+1)<argc ) {
 		shift;
 		cout<<V3Options::getenvBuiltins(argv[i])<<endl;
@@ -1252,6 +1256,7 @@ V3Options::V3Options() {
 
     m_convergeLimit = 100;
     m_dumpTree = 0;
+    m_gateStmts = 100;
     m_ifDepth = 0;
     m_inlineMult = 2000;
     m_moduleRecursion = 100;

src/V3Options.h

@@ -107,6 +107,7 @@ class V3Options {
 
     int		m_convergeLimit;// main switch: --converge-limit
     int		m_dumpTree;	// main switch: --dump-tree
+    int         m_gateStmts;    // main switch: --gate-stmts
     int		m_ifDepth;	// main switch: --if-depth
     int		m_inlineMult;	// main switch: --inline-mult
     int		m_moduleRecursion;// main switch: --module-recursion-depth
@@ -254,6 +255,7 @@ class V3Options {
 
     int	   convergeLimit() const { return m_convergeLimit; }
     int    dumpTree() const { return m_dumpTree; }
+    int    gateStmts() const { return m_gateStmts; }
     int	   ifDepth() const { return m_ifDepth; }
     int	   inlineMult() const { return m_inlineMult; }
     int	   moduleRecursionDepth() const { return m_moduleRecursion; }

src/V3Tristate.cpp

@@ -1117,10 +1117,12 @@ class TristateVisitor : public TristateBaseVisitor {
 	    }
 	    // Create new output pin
 	    AstAssignW* outAssignp = NULL;  // If reconnected, the related assignment
-	    AstPin* outpinp;
-	    {
-		AstVar* outModVarp = (AstVar*) nodep->modVarp()->user4p();
-		if (!outModVarp) nodep->v3fatalSrc("Unlinked");
+            AstPin* outpinp = NULL;
+            AstVar* outModVarp = (AstVar*) nodep->modVarp()->user4p();
+            if (!outModVarp) {
+                // At top, no need for __out as might be input only. Otherwise resolvable.
+                if (!m_modp->isTop()) nodep->v3fatalSrc("Unlinked");
+            } else {
 		AstNode* outexprp = nodep->exprp()->cloneTree(false);  // Note has lvalue() set
 		outpinp = new AstPin(nodep->fileline(),
 				     nodep->pinNum(),
@@ -1153,14 +1155,19 @@ class TristateVisitor : public TristateBaseVisitor {
 	    // Connect enable to output signal
 	    AstVarRef* exprrefp;  // Tristate variable that the Pin's expression refers to
 	    if (!outAssignp) {
-		exprrefp = outpinp->exprp()->castVarRef();
+                if (!outpinp) {
+                    exprrefp = NULL;  // Primary input only
+                } else {
+                    // pinReconnect should have converted this
+                    exprrefp = outpinp->exprp()->castVarRef();
+                    if (!exprrefp) nodep->v3error("Unsupported tristate port expression: "<<nodep->exprp()->prettyTypeName());
+                }
 	    } else {
+                // pinReconnect should have converted this
 		exprrefp = outAssignp->rhsp()->castVarRef();  // This should be the same var as the output pin
+                if (!exprrefp) nodep->v3error("Unsupported tristate port expression: "<<nodep->exprp()->prettyTypeName());
 	    }
-	    if (!exprrefp) { // deal with simple varref port
-		// pinReconnect should have converted this
-		nodep->v3error("Unsupported tristate port expression: "<<nodep->exprp()->prettyTypeName());
-	    } else {
+            if (exprrefp) {
 		UINFO(9,"outref "<<exprrefp<<endl);
 		exprrefp->user1p(enrefp);  // Mark as now tristated; iteration will pick it up from there
 		if (!outAssignp) {

src/Verilator.cpp

@@ -476,6 +476,7 @@ void process () {
 	V3Const::constifyCpp(v3Global.rootp());
 	V3Subst::substituteAll(v3Global.rootp());
     }
+
     if (!v3Global.opt.xmlOnly()
 	&& v3Global.opt.oSubstConst()) {
 	// Constant folding of substitutions

src/verilog.l

@@ -437,6 +437,7 @@ vnum	{vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   "always_comb"		{ FL; return yALWAYS_COMB; }
   "always_ff"		{ FL; return yALWAYS_FF; }
   "always_latch"	{ FL; return yALWAYS_LATCH; }
+  "assume"		{ FL; return yASSUME; }
   "assert"		{ FL; return yASSERT; }
   "bind"		{ FL; return yBIND; }
   "bit"			{ FL; return yBIT; }
@@ -490,7 +491,6 @@ vnum	{vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   /* Note assert_strobe was in SystemVerilog 3.1, but removed for SystemVerilog 2005 */
   "$root"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "alias"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
-  "assume"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "before"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "bins"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "binsof"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }

src/verilog.y

@@ -302,6 +302,7 @@ class AstSenTree;
 %token<fl>		yALWAYS_LATCH	"always_latch"
 %token<fl>		yAND		"and"
 %token<fl>		yASSERT		"assert"
+%token<fl>		yASSUME		"assume"
 %token<fl>		yASSIGN		"assign"
 %token<fl>		yAUTOMATIC	"automatic"
 %token<fl>		yBEGIN		"begin"
@@ -3667,6 +3668,7 @@ clocking_declaration<nodep>:		// IEEE: clocking_declaration  (INCOMPLETE)
 
 labeledStmt<nodep>:
 		immediate_assert_statement		{ $$ = $1; }
+	|	immediate_assume_statement		{ $$ = $1; }
 	;
 
 concurrent_assertion_item<nodep>:	// IEEE: concurrent_assertion_item
@@ -3698,6 +3700,13 @@ immediate_assert_statement<nodep>:	// ==IEEE: immediate_assert_statement
 	|	yASSERT '(' expr ')' stmtBlock yELSE stmtBlock		{ $$ = new AstVAssert($1,$3,$5,$7);   }
 	;
 
+immediate_assume_statement<nodep>:	// ==IEEE: immediate_assume_statement
+	//				// action_block expanded here, for compatibility with AstVAssert
+		yASSUME '(' expr ')' stmtBlock %prec prLOWER_THAN_ELSE	{ $$ = new AstVAssert($1,$3,$5, GRAMMARP->createDisplayError($1)); }
+	|	yASSUME '(' expr ')'           yELSE stmtBlock		{ $$ = new AstVAssert($1,$3,NULL,$6); }
+	|	yASSUME '(' expr ')' stmtBlock yELSE stmtBlock		{ $$ = new AstVAssert($1,$3,$5,$7);   }
+	;
+
 //************************************************
 // Covergroup
 

test_regress/Makefile_obj

@@ -59,7 +59,7 @@ endif
 
 #Default link, using normal make rules
 #$(VM_PREFIX): $(VK_GLOBAL_OBJS) $(VK_OBJS)
-#	$(LINK) $(LDFLAGS) -g $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) 2>&1 | c++filt
+#	$(LINK) $(LDFLAGS) -g $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) 2>&1
 
 #Our own compile rules; Faster compile, all in one file
 $(VM_PREFIX)__ALLboth.cpp: $(VK_CLASSES_CPP) $(VK_SUPPORT_CPP)
@@ -70,5 +70,5 @@ $(VM_PREFIX)__ALLboth.o: $(VM_PREFIX)__ALLboth.cpp
 
 ifneq ($(MAKE_MAIN),0)
    $(VM_PREFIX): $(VM_PREFIX)__ALLboth.o
-	$(LINK) $(LDFLAGS) -g $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) 2>&1 | c++filt
+	$(LINK) $(LDFLAGS) -g $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) 2>&1
 endif

test_regress/driver.pl

@@ -663,7 +663,7 @@ sub compile {
     elsif ($param{vlt}) {
 	my @cmdargs = $self->compile_vlt_flags(%param);
 
-	if ($self->sc && !defined $ENV{SYSTEMC} && !defined $ENV{SYSTEMC_INCLUDE}) {
+	if ($self->sc && !$self->have_sc) {
 	    $self->skip("Test requires SystemC; ignore error since not installed\n");
 	    return 1;
 	}
@@ -911,6 +911,12 @@ sub sc {
     return $self->{sc};
 }
 
+sub have_sc {
+    #my $self = shift;
+    return 1 if (defined $ENV{SYSTEMC} || defined $ENV{SYSTEMC_INCLUDE});
+    return 0;
+}
+
 #----------------------------------------------------------------------
 
 sub run {
@@ -1071,7 +1077,8 @@ sub _make_main {
     print $fh "// General headers\n";
     print $fh "#include \"verilated.h\"\n";
     print $fh "#include \"systemc.h\"\n" if $self->sc;
-    print $fh "#include \"verilated_vcd_c.h\"\n" if $self->{trace};
+    print $fh "#include \"verilated_vcd_c.h\"\n" if $self->{trace} && !$self->sc;
+    print $fh "#include \"verilated_vcd_sc.h\"\n" if $self->{trace} && $self->sc;
     print $fh "#include \"verilated_save.h\"\n" if $self->{savable};
 
     print $fh "$VM_PREFIX * topp;\n";
@@ -1132,7 +1139,8 @@ sub _make_main {
 	$fh->print("\n");
 	$fh->print("#if VM_TRACE\n");
 	$fh->print("    Verilated::traceEverOn(true);\n");
-	$fh->print("    VerilatedVcdC* tfp = new VerilatedVcdC;\n");
+        $fh->print("    VerilatedVcdC* tfp = new VerilatedVcdC;\n") if !$self->sc;
+        $fh->print("    VerilatedVcdSc* tfp = new VerilatedVcdSc;\n") if $self->sc;
 	$fh->print("    topp->trace (tfp, 99);\n");
 	$fh->print("    tfp->open (\"$self->{obj_dir}/simx.vcd\");\n");
 	if ($self->{trace} && !$self->sc) {

test_regress/t/t_altera_lpm_abs.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_add_sub.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_and.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_bustri.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_clshift.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_compare.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_constant.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_counter.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_decode.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_divide.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_ff.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_fifo.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_fifo_dc.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_inv.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_latch.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_mult.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_mux.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_or.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_ram_dp.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_ram_dq.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_ram_io.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_rom.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_shiftreg.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_xor.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_assert_basic.v

@@ -32,6 +32,7 @@ module t (/*AUTOARG*/
 `ifdef FAILING_ASSERTIONS
 	    assert (0) else $info;
 	    assert (0) else $info("Info message");
+	    assume (0) else $info("Info message from failing assumption");
 	    assert (0) else $info("Info message, cyc=%d", cyc);
 	    InWarningBlock: assert (0) else $warning("Warning.... 1.0=%f 2.0=%f", 1.0, 2.0);
 	    InErrorBlock: assert (0) else $error("Error....");

test_regress/t/t_gate_chained.pl

@@ -0,0 +1,56 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+use IO::File;
+
+sub gen {
+    my $filename = shift;
+
+    my $fh = IO::File->new(">$filename");
+    $fh->print("// Generated by t_gate_chained.pl\n");
+    $fh->print("module t (clk,i,sel,o);\n");
+    $fh->print("  input clk;\n");
+    $fh->print("  input [63:0] i;\n");
+    $fh->print("  input [15:0] sel;\n");
+    $fh->print("  output [63:0] o;\n");
+    $fh->print("\n");
+    my $prev = "i";
+    my $n = 9000;
+    for (my $i=1; $i<$n; ++$i) {
+        $fh->printf("  wire [63:0] ass%04x = (sel == 16'h%04x) ? 64'h0 : $prev;\n", $i, $i);
+        $prev = sprintf("ass%04x", $i);
+    }
+
+    $fh->print("\n");
+    $fh->print("  wire [63:0] o = $prev;\n");
+
+    $fh->print("\n");
+    $fh->print("  always @ (posedge clk) begin\n");
+    $fh->print('    $write("*-* All Finished *-*\n");',"\n");
+    $fh->print('    $finish;',"\n");
+    $fh->print("  end\n");
+    $fh->print("endmodule\n");
+}
+
+top_filename("$Self->{obj_dir}/t_gate_chained.v");
+
+gen($Self->{top_filename});
+
+compile (
+    verilator_flags2=>["--stats --x-assign fast --x-initial fast"],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+# Must be <<9000 above to prove this worked
+file_grep ($Self->{stats}, qr/Optimizations, Gate sigs deleted\s+(\d+)/i, 8575);
+
+ok(1);
+1;

test_regress/t/t_interface_bind_public.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2004 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    verilator_flags2 => ['-public'],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_interface_bind_public.v

@@ -0,0 +1,129 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2018 by Alex Solomatnikov.
+
+interface hex2ram_if
+  (
+   input bit trigger
+   );
+
+   string    instance_path  = $sformatf("%m");
+   string    testfile       = "";
+   bit       has_testfile   = |($value$plusargs("testfile=%s", testfile));
+   bit       armed          = 1'b1;
+   bit       armed_trigger;
+
+   initial begin
+      $display("successfully bound hex2ram_if to %s", instance_path);
+      armed = has_testfile && 1'b1;
+   end
+
+   assign armed_trigger = armed && trigger;
+
+   always @(posedge armed_trigger) begin
+      $display("%m(%0t): saw deassertion of reset", $time);
+   end
+
+endinterface : hex2ram_if
+
+module t
+  (
+   clk
+   );
+
+   input clk /*verilator clocker*/;
+   bit reset;
+
+   wire      success;
+   SimpleTestHarness testHarness
+     (
+      .clk(clk),
+      .reset(reset),
+      .io_success(success)
+      );
+
+   integer   cyc=0;
+
+   always @ (posedge clk) begin
+      cyc = cyc + 1;
+      if (cyc<10) begin
+         reset <= '0;
+      end
+      else if (cyc<20) begin
+         reset <= '1;
+      end
+      else if (cyc<30) begin
+         reset <= '0;
+      end
+      else if (cyc==99) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+endmodule
+
+bind testharness_ext  hex2ram_if i_hex2ram (.trigger(!t.reset));
+
+module testharness_ext
+  (
+   input          W0_clk,
+   input [24:0]   W0_addr,
+   input          W0_en,
+   input [127:0]  W0_data,
+   input [0:0]    W0_mask,
+   input          R0_clk,
+   input [24:0]   R0_addr,
+   input          R0_en,
+   output [127:0] R0_data
+   );
+
+   reg [24:0]     reg_R0_addr;
+   wire [127:0]   R0_rdata_mask;
+   reg [127:0]    ram [33554431:0];
+   wire [127:0]   W0_wdata_mask;
+
+   always @(posedge R0_clk)
+     if (R0_en) reg_R0_addr <= R0_addr;
+
+   always @(posedge W0_clk)
+     if (W0_en) begin
+        if (W0_mask[0]) ram[W0_addr] <= W0_data ^ W0_wdata_mask;
+     end
+   assign R0_data = ram[reg_R0_addr] ^ R0_rdata_mask;;
+   assign R0_rdata_mask = 0;
+   assign W0_wdata_mask = 0;
+
+endmodule
+
+module SimpleTestHarness
+  (
+   input  clk,
+   input  reset,
+   output io_success);
+
+   wire [24:0] testharness_ext_R0_addr;
+   wire        testharness_ext_R0_en;
+   wire        testharness_ext_R0_clk;
+   wire [127:0] testharness_ext_R0_data;
+   wire [24:0]  testharness_ext_W0_addr;
+   wire         testharness_ext_W0_en;
+   wire         testharness_ext_W0_clk;
+   wire [127:0] testharness_ext_W0_data;
+   wire [0:0]  testharness_ext_W0_mask;
+
+   testharness_ext testharness_ext
+     (
+      .R0_addr(testharness_ext_R0_addr),
+      .R0_en(testharness_ext_R0_en),
+      .R0_clk(testharness_ext_R0_clk),
+      .R0_data(testharness_ext_R0_data),
+      .W0_addr(testharness_ext_W0_addr),
+      .W0_en(testharness_ext_W0_en),
+      .W0_clk(testharness_ext_W0_clk),
+      .W0_data(testharness_ext_W0_data),
+      .W0_mask(testharness_ext_W0_mask)
+      );
+
+endmodule

test_regress/t/t_math_real_public.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    verilator_flags2 => ['--cc --public'],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_math_real_public.v

@@ -0,0 +1,21 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2018 by Alex Solomatnikov
+
+module t;
+   sub #(.REAL(2.0)) sub;
+endmodule
+
+module sub ();
+   timeunit 1ns;
+   timeprecision 1ps;
+
+   parameter REAL = 0.0;
+
+   initial begin
+      $display("REAL %g", REAL);
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule

test_regress/t/t_param_public.cpp

@@ -16,7 +16,7 @@ int main (int argc, char *argv[]) {
     Verilated::debug(0);
 
     // Make sure public tag worked
-    if (static_cast<bool>(Vt_param_public_p::INPACK)) {}
+    if (static_cast<int>(Vt_param_public_p::INPACK) != 0) {}
 
     for (int i = 0; i < 10; i++) {
 	topp->eval();

test_regress/t/t_trace_ena_cc.out

@@ -0,0 +1,89 @@
+$version Generated by VerilatedVcd $end
+$date Sat Jan 27 15:03:24 2018
+ $end
+$timescale   1ns $end
+
+ $scope module top $end
+  $var wire  1 ' clk $end
+  $scope module t $end
+   $var wire 32 $ c_trace_on [31:0] $end
+   $var wire  1 ' clk $end
+   $var wire 32 # cyc [31:0] $end
+   $var real 64 % r $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000001 #
+b00000000000000000000000000000000 $
+r0 %
+0'
+#10
+b00000000000000000000000000000010 #
+r0.1 %
+1'
+#15
+0'
+#20
+b00000000000000000000000000000011 #
+b00000000000000000000000000000001 $
+r0.2 %
+1'
+#25
+0'
+#30
+b00000000000000000000000000000100 #
+b00000000000000000000000000000010 $
+r0.3 %
+1'
+#35
+0'
+#40
+b00000000000000000000000000000101 #
+b00000000000000000000000000000011 $
+r0.4 %
+1'
+#45
+0'
+#50
+b00000000000000000000000000000110 #
+b00000000000000000000000000000100 $
+r0.5 %
+1'
+#55
+0'
+#60
+b00000000000000000000000000000111 #
+b00000000000000000000000000000101 $
+r0.6 %
+1'
+#65
+0'
+#70
+b00000000000000000000000000001000 #
+b00000000000000000000000000000110 $
+r0.7 %
+1'
+#75
+0'
+#80
+b00000000000000000000000000001001 #
+b00000000000000000000000000000111 $
+r0.7999999999999999 %
+1'
+#85
+0'
+#90
+b00000000000000000000000000001010 #
+b00000000000000000000000000001000 $
+r0.8999999999999999 %
+1'
+#95
+0'
+#100
+b00000000000000000000000000001011 #
+b00000000000000000000000000001001 $
+r0.9999999999999999 %
+1'

test_regress/t/t_trace_ena_cc.pl

@@ -10,18 +10,20 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 top_filename("t/t_trace_ena.v");
 
 compile (
-	 verilator_flags2 => ['-trace'],
-	 );
+    verilator_flags2 => ['-trace'],
+    );
 
 execute (
-	 check_finished=>1,
-	 );
+    check_finished=>1,
+    );
 
 if ($Self->{vlt}) {
     file_grep     ("$Self->{obj_dir}/V$Self->{name}__Trace__Slow.cpp", qr/c_trace_on\"/x);
     file_grep_not ("$Self->{obj_dir}/V$Self->{name}__Trace__Slow.cpp", qr/_trace_off\"/x);
     file_grep     ("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x);
     file_grep_not ("$Self->{obj_dir}/simx.vcd", qr/inside_sub/x);
+
+    vcd_identical("$Self->{obj_dir}/simx.vcd", "t/$Self->{name}.out");
 }
 
 ok(1);

test_regress/t/t_trace_ena_sc.out

@@ -0,0 +1,164 @@
+$version Generated by VerilatedVcd $end
+$date Mon Jan 29 09:34:59 2018
+ $end
+$timescale   1ps $end
+
+ $scope module top $end
+  $scope module t $end
+   $var wire 32 % c_trace_on [31:0] $end
+   $var wire  1 # clk $end
+   $var wire 32 $ cyc [31:0] $end
+   $var real 64 & r $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+0#
+b00000000000000000000000000000001 $
+b00000000000000000000000000000000 %
+r0 &
+#10000
+1#
+b00000000000000000000000000000010 $
+r0.1 &
+#11000
+#12000
+#13000
+#14000
+#15000
+0#
+#16000
+#17000
+#18000
+#19000
+#20000
+1#
+b00000000000000000000000000000011 $
+b00000000000000000000000000000001 %
+r0.2 &
+#21000
+#22000
+#23000
+#24000
+#25000
+0#
+#26000
+#27000
+#28000
+#29000
+#30000
+1#
+b00000000000000000000000000000100 $
+b00000000000000000000000000000010 %
+r0.3 &
+#31000
+#32000
+#33000
+#34000
+#35000
+0#
+#36000
+#37000
+#38000
+#39000
+#40000
+1#
+b00000000000000000000000000000101 $
+b00000000000000000000000000000011 %
+r0.4 &
+#41000
+#42000
+#43000
+#44000
+#45000
+0#
+#46000
+#47000
+#48000
+#49000
+#50000
+1#
+b00000000000000000000000000000110 $
+b00000000000000000000000000000100 %
+r0.5 &
+#51000
+#52000
+#53000
+#54000
+#55000
+0#
+#56000
+#57000
+#58000
+#59000
+#60000
+1#
+b00000000000000000000000000000111 $
+b00000000000000000000000000000101 %
+r0.6 &
+#61000
+#62000
+#63000
+#64000
+#65000
+0#
+#66000
+#67000
+#68000
+#69000
+#70000
+1#
+b00000000000000000000000000001000 $
+b00000000000000000000000000000110 %
+r0.7 &
+#71000
+#72000
+#73000
+#74000
+#75000
+0#
+#76000
+#77000
+#78000
+#79000
+#80000
+1#
+b00000000000000000000000000001001 $
+b00000000000000000000000000000111 %
+r0.7999999999999999 &
+#81000
+#82000
+#83000
+#84000
+#85000
+0#
+#86000
+#87000
+#88000
+#89000
+#90000
+1#
+b00000000000000000000000000001010 $
+b00000000000000000000000000001000 %
+r0.8999999999999999 &
+#91000
+#92000
+#93000
+#94000
+#95000
+0#
+#96000
+#97000
+#98000
+#99000
+#100000
+1#
+b00000000000000000000000000001011 $
+b00000000000000000000000000001001 %
+r0.9999999999999999 &
+#101000
+#102000
+#103000
+#104000

test_regress/t/t_trace_ena_sc.pl

@@ -7,19 +7,26 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
 
-top_filename("t/t_trace_ena.v");
+if (!$Self->have_sc) {
+    $Self->skip("No SystemC installed");
+}
+else {
+    top_filename("t/t_trace_ena.v");
 
-compile (
-	 verilator_flags2 => ['-trace -sc'],
-	 );
+    compile (
+        verilator_flags2 => ['-trace -sc'],
+        );
 
-execute (
-	 check_finished=>1,
-	 );
+    execute (
+        check_finished=>1,
+        );
 
-if ($Self->{vlt}) {
-    # Note more checks in _cc.pl
-    file_grep     ("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x);
+    if ($Self->{vlt}) {
+        # Note more checks in _cc.pl
+        file_grep     ("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x);
+
+        vcd_identical("$Self->{obj_dir}/simx.vcd", "t/$Self->{name}.out");
+    }
 }
 
 ok(1);

test_regress/t/t_tri_inz.cpp

@@ -0,0 +1,47 @@
+// -*- mode: C++; c-file-style: "cc-mode" -*-
+
+#include "Vt_tri_inz.h"
+
+Vt_tri_inz* tb = NULL;
+bool pass = true;
+
+double sc_time_stamp() {
+    return 0;
+}
+
+void checkone(const char* name, int got, int exp) {
+    if (got != exp) {
+        printf("%%Error: For %s got=%d exp=%d\n", name, got, exp);
+        pass = false;
+    }
+}
+
+void check(int d, int en, int exp0, int exp1, int expx, int expz) {
+    tb->d = d;
+    tb->d__en0 = en;
+    tb->eval();
+#ifdef TEST_VERBOSE
+    printf("Drive d=%d en=%d got0=%d/1=%d/x=%d/z=%d  exp0=%d/1=%d/x=%d/z=%d\n",
+           d, en, tb->ext0, tb->ext1, tb->extx, tb->extz, exp0, exp1, expx, expz);
+#endif
+    if (!expz) checkone("ext0", tb->ext0, exp0);
+    if (!expz) checkone("ext1", tb->ext1, exp1);
+    checkone("extx", tb->extx, expx);
+    checkone("extz", tb->extz, expz);
+}
+
+int main() {
+    Verilated::debug(0);
+    tb  = new Vt_tri_inz("tb");
+    check(0, 1,   1,0,0,0);
+    check(1, 1,   0,1,0,0);
+    check(0, 0,   0,0,0,1);
+
+    if (pass) {
+        VL_PRINTF("*-* All Finished *-*\n");
+        tb->final();
+    } else {
+        vl_fatal(__FILE__,__LINE__,"top", "Unexpected results from t_tri_inz\n");
+    }
+    return 0;
+}

test_regress/t/t_tri_inz.pl

@@ -0,0 +1,23 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2018 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+compile (
+    make_top_shell => 0,
+    make_main => 0,
+    verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_tri_inz.v

@@ -0,0 +1,15 @@
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2018 by Wilson Snyder
+
+module top
+  (input d,
+   output ext0,
+   output ext1,
+   output extx,
+   output extz);
+
+   assign ext0 = (d === 1'b0);
+   assign ext1 = (d === 1'b1);
+   assign extx = (d === 1'bx);
+   assign extz = (d === 1'bz);
+endmodule

test_regress/t/t_verilated_all_newest.pl

@@ -14,6 +14,7 @@ my $root = "..";
 compile (
     # Can't use --coverage and --savable together, so cheat and compile inline
     verilator_flags2 => ['--cc --coverage-toggle --coverage-line --coverage-user --trace --vpi $root/include/verilated_save.cpp'],
+    make_flags => 'DRIVER_STD=newest',
     );
 
 execute (

test_regress/t/t_vlcov_merge.pl

@@ -17,5 +17,14 @@ $Self->run(cmd=>["../bin/verilator_coverage",
                  "t/t_vlcov_data_d.dat",
            ],
     );
-ok(files_identical("$Self->{obj_dir}/coverage.dat", "t/$Self->{name}.out"));
+
+# Older clib's didn't properly sort maps, but the coverage data doesn't
+# really care about ordering. So avoid false failures by sorting.
+$Self->run(cmd=>["sort",
+                 "$Self->{obj_dir}/coverage.dat",
+                 "> $Self->{obj_dir}/coverage-sort.dat",
+           ],
+    );
+
+ok(files_identical("$Self->{obj_dir}/coverage-sort.dat", "t/$Self->{name}.out"));
 1;

test_regress/t/t_xml_first.out

@@ -43,7 +43,7 @@
       <var fl="e37" name="q" dtype_id="2"/>
       <always fl="e39">
         <sentree fl="e39">
-          <senitem fl="e39">
+          <senitem fl="e39" edgeType="POS">
             <varref fl="e39" name="clk" dtype_id="1"/>
           </senitem>
         </sentree>