Version bump

Fix internal error on functions called as SV tasks.

Changes

@@ -3,6 +3,26 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilator 3.811 2011/02/14
+
+**** Report errors on duplicated or empty pins, bug321.  [Christian Leber]
+
+**** Report error on function call output tied to constant.  [Bernard Deadman]
+
+**** Throw UNUSED/UNDRIVEN only once per net in a parametrized module.
+
+**** Fix internal error on functions called as SV tasks.  [Bernard Deadman]
+
+**** Fix internal error on non-inlined inout pins.  [Jeff Winston]
+
+**** Fix false BLKSEQ on non-unrolled for loop indexes.  [Jeff Winston]
+
+**** Fix block comment not separating identifiers, bug311. [Gene Sullivan]
+
+**** Fix warnings to point to lowest net usage, not upper level ports.
+
+**** Fix error on constants connected to outputs, bug323.  [Christian Leber]
+
 * Verilator 3.810 2011/01/03
 
 **   Add limited support for VPI access to public signals, see docs.

TODO

@@ -67,6 +67,10 @@ Usability:
 	  	    #### non-comment lines, ##### ops, ### KB model size
 	* Default the --l2name to remove extra "v" level of hierarchy (flag to make "top")
 
+Lint:
+	* CDCRSTLOGIC should allow filtering with paths
+	  "waive CDCRSTLOGIC --from a.b.sig  --to a.c.sig --via OR"
+
 Internal Code:
 	* Eliminate the AstNUser* passed to all visitors; its only needed in V3Width,
 	  and removing it will speed up and simplify all the other code.

src/V3Ast.cpp

@@ -192,6 +192,7 @@ string AstNode::prettyName(const string& namein) {
 	}
     }
     if (pretty.substr(0,4) == "TOP.") pretty.replace(0,4,"");
+    if (pretty.substr(0,5) == "TOP->") pretty.replace(0,5,"");
     return pretty;
 }
 

src/V3AstNodes.cpp

@@ -611,6 +611,7 @@ void AstVar::dump(ostream& str) {
     }
     if (isUsedClock()) str<<" [C]";
     if (isSigPublic()) str<<" [P]";
+    if (isUsedLoopIdx()) str<<" [LOOP]"; 
     if (attrClockEn()) str<<" [aCLKEN]";
     if (attrIsolateAssign()) str<<" [aISO]";
     if (attrFileDescr()) str<<" [aFD]";

src/V3AstNodes.h

@@ -912,7 +912,9 @@ public:
 	,m_name(name), m_svImplicit(false) {
 	m_pinNum = pinNum;
 	m_modVarp = NULL;
-	setNOp1p(exprp); }
+	setNOp1p(exprp);
+	if (exprp) widthSignedFrom(exprp);
+    }
     ASTNODE_NODE_FUNCS(Pin, PIN)
     virtual void dump(ostream& str);
     virtual bool broken() const { return (m_modVarp && !m_modVarp->brokeExists()); }
@@ -921,7 +923,7 @@ public:
     bool	dotStar()	const { return name() == ".*"; }	// Special fake name for .* connections until linked
     int		pinNum()	const { return m_pinNum; }
     void	exprp(AstNode* nodep) { addOp1p(nodep); }
-    AstNode*	exprp()		const { return op1p()->castNode(); }	// op1 = Expression connected to pin
+    AstNode*	exprp()		const { return op1p()->castNode(); }	// op1 = Expression connected to pin, NULL if unconnected
     AstVar*	modVarp()	const { return m_modVarp; }		// [After Link] Pointer to variable
     void  	modVarp(AstVar* varp) { m_modVarp=varp; }
     bool	svImplicit()	const { return m_svImplicit; }

src/V3Begin.cpp

@@ -162,7 +162,7 @@ private:
 	    m_ifDepth = -1;
 	} else if (++m_ifDepth > v3Global.opt.ifDepth()) {
 	    nodep->v3warn(IFDEPTH,"Deep 'if' statement; suggest unique/priority to avoid slow logic");
-	    nodep->fileline()->warnOn(V3ErrorCode::IFDEPTH, false);  // Warn only once
+	    nodep->fileline()->modifyWarnOff(V3ErrorCode::IFDEPTH, true);  // Warn only once
 	    m_ifDepth = -1;
 	}
 	nodep->iterateChildren(*this);

src/V3Cdc.cpp

@@ -65,9 +65,9 @@ class CdcEitherVertex : public V3GraphVertex {
     AstNode*	m_nodep;
     AstSenTree*	m_srcDomainp;
     AstSenTree*	m_dstDomainp;
-    bool	m_srcDomainSet;
-    bool	m_dstDomainSet;
-    bool	m_asyncPath;
+    bool	m_srcDomainSet:1;
+    bool	m_dstDomainSet:1;
+    bool	m_asyncPath:1;
 public:
     CdcEitherVertex(V3Graph* graphp, AstScope* scopep, AstNode* nodep)
 	: V3GraphVertex(graphp), m_scopep(scopep), m_nodep(nodep)
@@ -109,11 +109,12 @@ public:
 };
 
 class CdcLogicVertex : public CdcEitherVertex {
-    bool	m_hazard;
-    bool	m_isFlop;
+    bool	m_hazard:1;
+    bool	m_isFlop:1;
 public:
     CdcLogicVertex(V3Graph* graphp, AstScope* scopep, AstNode* nodep, AstSenTree* sensenodep)
-	: CdcEitherVertex(graphp,scopep,nodep), m_hazard(false), m_isFlop(false)
+	: CdcEitherVertex(graphp,scopep,nodep)
+	, m_hazard(false), m_isFlop(false)
 	{ srcDomainp(sensenodep); dstDomainp(sensenodep); }
     virtual ~CdcLogicVertex() {}
     // Accessors
@@ -132,7 +133,7 @@ class CdcDumpVisitor : public CdcBaseVisitor {
 private:
     // NODE STATE
     //Entire netlist:
-    // {statement}Node::user3p	-> bool, indicating not hazard
+    // {statement}Node::user3	-> bool, indicating not hazard
     ofstream*		m_ofp;		// Output file
     string		m_prefix;
 
@@ -290,9 +291,12 @@ private:
     void setNodeHazard(AstNode* nodep) {
 	// Need to not clear if warnings are off (rather than when report it)
 	// as bypassing this warning may turn up another path that isn't warning off'ed.
+	// We can't modifyWarnOff here, as one instantiation might not be an issue until we find a hitting flop
+	// Furthermore, a module like a "Or" module would only get flagged once,
+	// even though the signals feeding it are radically different.
 	if (!m_domainp || m_domainp->hasCombo()) { // Source flop logic in a posedge block is OK for reset (not async though)
 	    if (m_logicVertexp && !nodep->fileline()->warnIsOff(V3ErrorCode::CDCRSTLOGIC)) {
-		UINFO(9,"Set hazard "<<nodep<<endl);
+		UINFO(8,"Set hazard "<<nodep<<endl);
 		m_logicVertexp->setHazard(nodep);
 	    }
 	}
@@ -335,7 +339,7 @@ private:
 	    if (CdcVarVertex* vvertexp = dynamic_cast<CdcVarVertex*>(itp)) {
 		if (vvertexp->cntAsyncRst()) {
 		    m_userGeneration++;  // Effectively a userClearVertices()
-		    UINFO(9, "   Trace One async: "<<vvertexp<<endl);
+		    UINFO(8, "   Trace One async: "<<vvertexp<<endl);
 		    // Twice, as we need to detect, then propagate
 		    CdcEitherVertex* markp = traceAsyncRecurse(vvertexp, false);
 		    if (markp) { // Mark is non-NULL if something bad on this path
@@ -351,7 +355,8 @@ private:
     }
 
     CdcEitherVertex* traceAsyncRecurse(CdcEitherVertex* vertexp, bool mark) {
-	// Return vertex of any hazardous stuff attached, or NULL if OK
+	// First pass: Return vertex of any hazardous stuff attached, or NULL if OK
+	// If first pass returns true, second pass calls asyncPath() on appropriate nodes
 	if (vertexp->user()>=m_userGeneration) return false;   // Processed - prevent loop
 	vertexp->user(m_userGeneration);
 

src/V3Delayed.cpp

@@ -345,9 +345,7 @@ private:
 	m_nextDlyp = NULL;
     }
     virtual void visit(AstVarRef* nodep, AstNUser*) {
-	if (!nodep->user2()) {  // Not done yet
-	    nodep->user2(true);
-
+	if (!nodep->user2Inc()) {  // Not done yet
 	    if (m_inDly && nodep->lvalue()) {
 		UINFO(4,"AssignDlyVar: "<<nodep<<endl);
 		markVarUsage(nodep->varScopep(), VU_DLY);

src/V3EmitV.cpp

@@ -74,7 +74,7 @@ class EmitVBaseVisitor : public EmitCBaseVisitor {
     virtual void visit(AstNodeFTask* nodep, AstNUser*) {
 	putfs(nodep, nodep->isFunction() ? "function":"task");
 	puts(" ");
-	puts(nodep->name());
+	puts(nodep->prettyName());
 	puts(";\n");
 	putqs(nodep, "begin\n");  // Only putfs the first time for each visitor; later for same node is putqs
 	nodep->stmtsp()->iterateAndNext(*this);
@@ -472,17 +472,17 @@ class EmitVBaseVisitor : public EmitCBaseVisitor {
     virtual void visit(AstTypedef* nodep, AstNUser*) {
 	putfs(nodep,"typedef ");
 	nodep->dtypep()->iterateAndNext(*this); puts(" ");
-	puts(nodep->name());
+	puts(nodep->prettyName());
 	puts(";\n");
     }
     virtual void visit(AstBasicDType* nodep, AstNUser*) {
 	if (nodep->isSigned()) putfs(nodep,"signed ");
 	putfs(nodep,nodep->prettyName());
-	if (nodep->rangep()) { nodep->rangep()->iterateAndNext(*this); puts(" "); }
+	if (nodep->rangep()) { puts(" "); nodep->rangep()->iterateAndNext(*this); puts(" "); }
     }
     virtual void visit(AstNodeFTaskRef* nodep, AstNUser*) {
-	if (nodep->dotted()!="") { putfs(nodep,nodep->dotted()); puts("."); puts(nodep->name()); }
-	else { putfs(nodep,nodep->name()); }
+	if (nodep->dotted()!="") { putfs(nodep,nodep->dotted()); puts("."); puts(nodep->prettyName()); }
+	else { putfs(nodep,nodep->prettyName()); }
 	puts("(");
 	nodep->pinsp()->iterateAndNext(*this);
 	puts(")");
@@ -520,7 +520,7 @@ class EmitVBaseVisitor : public EmitCBaseVisitor {
 	putfs(nodep,nodep->verilogKwd());
 	puts(" ");
 	nodep->dtypep()->iterateAndNext(*this); puts(" ");
-	puts(nodep->name());
+	puts(nodep->prettyName());
 	puts(";\n");
     }
     virtual void visit(AstActive* nodep, AstNUser*) {

src/V3Gate.cpp

@@ -719,6 +719,12 @@ private:
 		// Prevent a infinite loop...
 		substp->v3fatalSrc("Replacing node with itself; perhaps circular logic?");
 	    }
+	    // Which fileline() to use?
+	    // If replacing with logic, an error/warning is likely to want to point to the logic
+	    // IE what we're replacing with.
+	    // However a VARREF should point to the original as it's otherwise confusing
+	    // to throw warnings that point to a PIN rather than where the pin us used.
+	    if (substp->castVarRef()) substp->fileline(nodep->fileline());
 	    nodep->replaceWith(substp);
 	    nodep->deleteTree(); nodep=NULL;
 	}

src/V3Inline.cpp

@@ -140,6 +140,10 @@ private:
 		if (!connectRefp->castConst() && !connectRefp->castVarRef()) {
 		    pinp->v3fatalSrc("Unknown interconnect type; pinReconnectSimple should have cleared up\n");
 		}
+		if (pinNewVarp->isOutOnly() && connectRefp->castConst()) {
+		    pinp->v3error("Output port is connected to a constant pin, electrical short");
+		}
+
 		// Propagate any attributes across the interconnect
 		pinNewVarp->propagateAttrFrom(pinOldVarp);
 		if (connectRefp->castVarRef()) {

src/V3Link.cpp

@@ -55,9 +55,11 @@ private:
     //   AstNodeModule::user4p() // V3SymTable*    Module's Symbol table
     //   AstNodeFTask::user4p()	// V3SymTable*    Local Symbol table
     //   AstBegin::user4p()	// V3SymTable*    Local Symbol table
+    //   AstVar::user5p()	// AstPin*	  True if port attached to a pin
     AstUser2InUse	m_inuser2;
     AstUser3InUse	m_inuser3;
     AstUser4InUse	m_inuser4;
+    AstUser5InUse	m_inuser5;
 
     // ENUMS
     enum IdState {		// Which loop through the tree
@@ -498,6 +500,7 @@ private:
 		if (!taskp) { nodep->v3error("Can't find definition of task/function: "<<nodep->prettyName()); }
 		nodep->taskp(taskp);
 		nodep->packagep(packageFor(taskp));
+		if (taskp->castTask() && nodep->castFuncRef()) nodep->v3error("Illegal call of a task as a function: "<<nodep->prettyName());
 	    }
 	}
 	nodep->iterateChildren(*this);
@@ -551,6 +554,7 @@ private:
     virtual void visit(AstCell* nodep, AstNUser*) {
 	// Cell: Resolve its filename.  If necessary, parse it.
 	m_cellp = nodep;
+	AstNode::user5ClearTree();
 	if (m_idState==ID_FIND) {
 	    // Add to list of all cells, for error checking and defparam's
 	    findAndInsertAndCheck(nodep, nodep->name());
@@ -635,11 +639,26 @@ private:
 		nodep->v3error("Pin is not an in/out/inout/param: "<<nodep->prettyName());
 	    } else {
 		nodep->modVarp(refp);
+		if (refp->user5p() && refp->user5p()->castNode()!=nodep) {
+		    nodep->v3error("Duplicate pin connection: "<<nodep->prettyName());
+		    refp->user5p()->castNode()->v3error("... Location of original pin connection");
+		} else {
+		    refp->user5p(nodep);
+		}
+	    }
+	    if (!nodep->exprp()) {
+		// It's an empty pin connection, done with it.
+		// (We used to not create pins for these, but we'd miss
+		// warns.  Perhaps they should live even further...)
+		pushDeletep(nodep->unlinkFrBack()); nodep=NULL;
+		return;
 	    }
 	    nodep->iterateChildren(*this);
 	}
 	// Deal with implicit definitions - do before ID_RESOLVE stage as may be referenced above declaration
-	if (m_idState==ID_PARAM && !nodep->svImplicit()) {   // SV 19.11.3: .name pins don't allow implicit decls
+	if (m_idState==ID_PARAM
+	    && nodep->exprp() // Else specifically unconnected pin
+	    && !nodep->svImplicit()) {   // SV 19.11.3: .name pins don't allow implicit decls
 	    pinImplicitExprRecurse(nodep->exprp());
 	}
 	// Early return() above when deleted

src/V3LinkCells.cpp

@@ -193,6 +193,18 @@ private:
 		new V3GraphEdge(&m_graph, vertex(m_modp), vertex(modp), 1, false);
 	    }
 	}
+	// Remove AstCell(AstPin("",NULL)), it's a side effect of how we parse "()"
+	// the empty middle is identical to the empty rule that must find pins in "(,)".
+	if (nodep->pinsp() && !nodep->pinsp()->nextp()
+	    && nodep->pinsp()->name() == ""
+	    && !nodep->pinsp()->exprp()) {
+	    pushDeletep(nodep->pinsp()->unlinkFrBackWithNext());
+	}
+	if (nodep->paramsp() && !nodep->paramsp()->nextp()
+	    && nodep->paramsp()->name() == ""
+	    && !nodep->paramsp()->exprp()) {
+	    pushDeletep(nodep->paramsp()->unlinkFrBackWithNext());
+	}
 	// Convert .* to list of pins
 	bool pinStar = false;
 	for (AstPin* nextp, *pinp = nodep->pinsp(); pinp; pinp=nextp) {

src/V3LinkJump.cpp

@@ -50,6 +50,7 @@ private:
     AstModule*		m_modp;		// Current module
     AstNodeFTask* 	m_ftaskp;	// Current function/task
     AstWhile*	 	m_loopp;	// Current loop
+    bool		m_loopInc;	// In loop increment
     int			m_repeatNum;	// Repeat counter
     BeginStack		m_beginStack;	// All begin blocks above current node
     
@@ -136,6 +137,7 @@ private:
 				  AstLogicPacked(), 32);
 	varp->isSigned(true);
 	varp->dtypep()->isSigned(true);
+	varp->usedLoopIdx(true);
 	m_modp->addStmtp(varp);
 	AstNode* initsp = new AstAssign(nodep->fileline(), new AstVarRef(nodep->fileline(), varp, true),
 					countp);
@@ -158,8 +160,15 @@ private:
     virtual void visit(AstWhile* nodep, AstNUser*) {
 	// Don't need to track AstRepeat/AstFor as they have already been converted
 	AstWhile* lastLoopp = m_loopp;
+	bool lastInc = m_loopInc;
 	m_loopp = nodep;
-	nodep->iterateChildren(*this);
+	m_loopInc = false;
+	nodep->precondsp()->iterateAndNext(*this);
+	nodep->condp()->iterateAndNext(*this);
+	nodep->bodysp()->iterateAndNext(*this);
+	m_loopInc = true;
+	nodep->incsp()->iterateAndNext(*this);
+	m_loopInc = lastInc;
 	m_loopp = lastLoopp;
     }
     virtual void visit(AstReturn* nodep, AstNUser*) {
@@ -202,7 +211,11 @@ private:
 	}
 	nodep->unlinkFrBack(); pushDeletep(nodep); nodep=NULL;
     }
+    virtual void visit(AstVarRef* nodep, AstNUser*) {
+	if (m_loopInc && nodep->varp()) nodep->varp()->usedLoopIdx(true);
+    }
 
+    virtual void visit(AstConst* nodep, AstNUser*) {}
     virtual void visit(AstNode* nodep, AstNUser*) {
 	nodep->iterateChildren(*this);
     }
@@ -212,6 +225,7 @@ public:
 	m_modp = NULL;
 	m_ftaskp = NULL;
 	m_loopp = NULL;
+	m_loopInc = false;
 	m_repeatNum = 0;
 	nodep->accept(*this);
     }

src/V3LinkParse.cpp

@@ -33,6 +33,7 @@
 #include <cstdarg>
 #include <unistd.h>
 #include <map>
+#include <set>
 #include <algorithm>
 #include <vector>
 
@@ -47,11 +48,14 @@ class LinkParseVisitor : public AstNVisitor {
 private:
     // NODE STATE
     // Cleared on netlist
-    //  AstNode::user()		-> bool.  True if processed
+    //  AstNode::user1()	-> bool.  True if processed
+    //  AstNode::user2()	-> bool.  True if fileline recomputed
     AstUser1InUse	m_inuser1;
+    AstUser2InUse	m_inuser2;
 
     // TYPES
     typedef map <pair<void*,string>,AstTypedef*> ImplTypedefMap;
+    typedef set <FileLine*> FileLineSet;
 
     // STATE
     string	m_dotText;	// Dotted module text we are building for a dotted node, passed up
@@ -60,6 +64,7 @@ private:
     AstText*	m_baseTextp;	// Lowest TEXT node that needs replacement with varref
     AstVar*	m_varp;		// Variable we're under
     ImplTypedefMap	m_implTypedef;	// Created typedefs for each <container,name>
+    FileLineSet		m_filelines;	// Filelines that have been seen
 
     // METHODS
     static int debug() {
@@ -68,6 +73,21 @@ private:
 	return level;
     }
 
+    void cleanFileline(AstNode* nodep) {
+	if (!nodep->user2Inc()) {  // Process once
+	    // We make all filelines unique per AstNode.  This allows us to
+	    // later turn off messages on a fileline when an issue is found
+	    // so that messages on replicated blocks occur only once,
+	    // without suppressing other token's messages as a side effect.
+	    // We could have verilog.l create a new one on every token,
+	    // but that's a lot more structures than only doing AST nodes.
+	    if (m_filelines.find(nodep->fileline()) != m_filelines.end()) {
+		nodep->fileline(new FileLine(nodep->fileline()));
+	    }
+	    m_filelines.insert(nodep->fileline());
+	}
+    }
+
     void checkExpected(AstNode* nodep) {
 	if (m_exp != AstParseRefExp::PX_NONE) {
 	    nodep->v3fatalSrc("Tree syntax error: Not expecting "<<nodep->type()<<" under a "<<nodep->backp()->type());
@@ -78,6 +98,7 @@ private:
     // VISITs
     virtual void visit(AstNodeFTaskRef* nodep, AstNUser*) {
 	if (!nodep->user1Inc()) {  // Process only once.
+	    cleanFileline(nodep);
 	    UINFO(5,"   "<<nodep<<endl);
 	    checkExpected(nodep);
 	    // Due to a need to get the arguments, the ParseRefs are under here,
@@ -141,6 +162,7 @@ private:
     }
     virtual void visit(AstDot* nodep, AstNUser*) {
 	UINFO(5,"     "<<nodep<<endl);
+	cleanFileline(nodep);
 	if (m_inModDot) { // Already under dot, so this is {modulepart} DOT {modulepart}
 	    m_dotText = "";
 	    nodep->lhsp()->iterateAndNext(*this);
@@ -165,6 +187,7 @@ private:
     }
     virtual void visit(AstSelBit* nodep, AstNUser*) {
 	if (!nodep->user1Inc()) {  // Process only once.
+	    cleanFileline(nodep);
 	    if (m_inModDot) { // Already under dot, so this is {modulepart} DOT {modulepart}
 		m_dotText = "";
 		nodep->lhsp()->iterateAndNext(*this);
@@ -193,6 +216,7 @@ private:
     virtual void visit(AstNodePreSel* nodep, AstNUser*) {
 	// Excludes simple AstSel, see above
 	if (!nodep->user1Inc()) {  // Process only once.
+	    cleanFileline(nodep);
 	    if (m_inModDot) { // Already under dot, so this is {modulepart} DOT {modulepart}
 		nodep->v3error("Syntax Error: Range ':', '+:' etc are not allowed in the cell part of a dotted reference");
 	    } else if (m_exp==AstParseRefExp::PX_FUNC) {
@@ -215,6 +239,7 @@ private:
     }
     virtual void visit(AstText* nodep, AstNUser*) {
 	if (!nodep->user1Inc()) {  // Process only once.
+	    cleanFileline(nodep);
 	    if (m_exp != AstParseRefExp::PX_NONE) {
 		UINFO(7,"      "<<nodep<<endl);
 		if (m_inModDot) {  // Dotted part, just pass up
@@ -228,6 +253,7 @@ private:
     }
     virtual void visit(AstEnumItem* nodep, AstNUser*) {
 	// Expand ranges
+	cleanFileline(nodep);
 	nodep->iterateChildren(*this);
 	if (nodep->rangep()) {
 	    if (!nodep->rangep()->msbp()->castConst()
@@ -251,12 +277,14 @@ private:
 
 
     virtual void visit(AstVar* nodep, AstNUser*) {
+	cleanFileline(nodep);
 	m_varp = nodep;
 	nodep->iterateChildren(*this);
 	m_varp = NULL;
     }
 
     virtual void visit(AstAttrOf* nodep, AstNUser*) {
+	cleanFileline(nodep);
 	nodep->iterateChildren(*this);
 	if (nodep->attrType() == AstAttrType::VAR_CLOCK) {
 	    if (!m_varp) nodep->v3fatalSrc("Attribute not attached to variable");
@@ -303,6 +331,7 @@ private:
     virtual void visit(AstAlwaysPublic* nodep, AstNUser*) {
 	// AlwaysPublic was attached under a var, but it's a statement that should be
 	// at the same level as the var
+	cleanFileline(nodep);
 	nodep->iterateChildren(*this);
 	if (m_varp) {
 	    nodep->unlinkFrBack();
@@ -315,6 +344,7 @@ private:
     }
 
     virtual void visit(AstDefImplicitDType* nodep, AstNUser*) {
+	cleanFileline(nodep);
 	UINFO(8,"   DEFIMPLICIT "<<nodep<<endl);
 	// Must remember what names we've already created, and combine duplicates
 	// so that for "var enum {...} a,b" a & b will share a common typedef
@@ -351,6 +381,7 @@ private:
 
     virtual void visit(AstNode* nodep, AstNUser*) {
 	// Default: Just iterate
+	cleanFileline(nodep);
 	checkExpected(nodep);  // So we detect node types we forgot to list here
 	nodep->iterateChildren(*this);
     }

src/V3Param.cpp

@@ -131,8 +131,7 @@ private:
 
     // Make sure all parameters are constantified
     virtual void visit(AstVar* nodep, AstNUser*) {
-	if (!nodep->user5()) {
-	    nodep->user5(1);  // Mark done
+	if (!nodep->user5Inc()) {  // Process once
 	    nodep->iterateChildren(*this);
 	    if (nodep->isParam()) {
 		if (!nodep->hasSimpleInit()) { nodep->v3fatalSrc("Parameter without initial value"); }

src/V3PreProc.cpp

@@ -848,8 +848,13 @@ int V3PreProcImp::getStateToken() {
 		if (m_lexp->m_keepComments == KEEPCMT_SUB) {
 		    string rtn; rtn.assign(yyourtext(),yyourleng());
 		    comment(rtn);
-		} else {
+		    // Need to insure "foo/**/bar" becomes two tokens
+		    insertUnreadback (" ");
+		} else if (m_lexp->m_keepComments) {
 		    return (tok);
+		} else {
+		    // Need to insure "foo/**/bar" becomes two tokens
+		    insertUnreadback (" ");
 		}
 	    }
 	    // We're off or processed the comment specially.  If there are newlines

src/V3Task.cpp

@@ -380,7 +380,10 @@ private:
 		UINFO(9, "      pin "<<pinp<<endl);
 		pinp->unlinkFrBack();   // Relinked to assignment below
 		//
-		if (portp->isInout()) {
+		if ((portp->isInout()||portp->isOutput()) && pinp->castConst()) {
+		    pinp->v3error("Function/task output connected to constant instead of variable: "+portp->prettyName());
+		}
+		else if (portp->isInout()) {
 		    if (AstVarRef* varrefp = pinp->castVarRef()) {
 			// Connect to this exact variable
 			AstVarScope* localVscp = varrefp->varScopep(); if (!localVscp) varrefp->v3fatalSrc("Null var scope");
@@ -390,9 +393,6 @@ private:
 			pinp->v3warn(E_TASKNSVAR,"Unsupported: Function/task input argument is not simple variable");
 		    }
 		}
-		else if (portp->isOutput() && outvscp) {
-		    refp->v3error("Outputs not allowed in function declarations");
-		}
 		else if (portp->isOutput()) {
 		    // Make output variables
 		    // Correct lvalue; we didn't know when we linked
@@ -456,7 +456,7 @@ private:
 	    tempp->stmtsp()->unlinkFrBackWithNext(); tempp->deleteTree(); tempp=NULL;
 	}
 	//
-	if (debug()>=9) { beginp->dumpTree(cout,"-iotask: "); }
+	if (debug()>=9) { beginp->dumpTreeAndNext(cout,"-iotask: "); }
 	return beginp;
     }
 
@@ -481,7 +481,10 @@ private:
 	    } else {
 		UINFO(9, "     Port "<<portp<<endl);
 		UINFO(9, "      pin "<<pinp<<endl);
-		if (portp->isInout()) {
+		if ((portp->isInout()||portp->isOutput()) && pinp->castConst()) {
+		    pinp->v3error("Function/task output connected to constant instead of variable: "+portp->prettyName());
+		}
+		else if (portp->isInout()) {
 		    if (pinp->castVarRef()) {
 			// Connect to this exact variable
 		    } else {
@@ -536,7 +539,7 @@ private:
 	    ccallp->addArgsp(new AstVarRef(refp->fileline(), outvscp, true));
 	}
 
-	if (debug()>=9) { beginp->dumpTree(cout,"-nitask: "); }
+	if (debug()>=9) { beginp->dumpTreeAndNext(cout,"-nitask: "); }
 	return beginp;
     }
 
@@ -1011,40 +1014,22 @@ private:
 	nodep->iterateChildren(*this);
 	m_scopep = NULL;
     }
-    virtual void visit(AstTaskRef* nodep, AstNUser*) {
-	iterateIntoFTask(nodep->taskp());	// First, do hierarchical funcs
-	UINFO(4," Task REF   "<<nodep<<endl);
-	if (debug()>=9) { nodep->dumpTree(cout,"-inltask:"); }
-	// Create cloned statements
-	string namePrefix = "__Vtask_"+nodep->taskp()->shortName()+"__"+cvtToStr(m_modNCalls++);
-	AstNode* beginp;
-	if (m_statep->ftaskNoInline(nodep->taskp())) {
-	    beginp = createNonInlinedFTask(nodep, namePrefix, NULL);
-	} else {
-	    beginp = createInlinedFTask(nodep, namePrefix, NULL);
-	}
-	// Replace the ref
-	nodep->replaceWith(beginp);
-	nodep->deleteTree(); nodep=NULL;
-    }
-    virtual void visit(AstFuncRef* nodep, AstNUser*) {
-	UINFO(4," Func REF   "<<nodep<<endl);
-	if (debug()>=9) { nodep->dumpTree(cout,"-preref:"); }
-	// First, do hierarchical funcs
-	AstNodeFTask* funcp = nodep->taskp();
-	if (!funcp) nodep->v3fatalSrc("unlinked");
-	if (!funcp->isFunction()) nodep->v3fatalSrc("func reference to non-function");
-	if (!m_scopep) nodep->v3fatalSrc("func ref not under scope");
-	// Inline func refs in the function
-	iterateIntoFTask(funcp);
-	// Create output variable
-	string namePrefix = "__Vfunc_"+nodep->taskp()->shortName()+"__"+cvtToStr(m_modNCalls++);
-	AstVarScope* outvscp = createVarScope (funcp->fvarp()->castVar(),
-					       namePrefix+"__Vfuncout");
-	// Create cloned statements
-	if (debug()>=9) { nodep->taskp()->dumpTree(cout,"-oldfunc:"); }
+    virtual void visit(AstNodeFTaskRef* nodep, AstNUser*) {
 	if (!nodep->taskp()) nodep->v3fatalSrc("Unlinked?");
-
+	iterateIntoFTask(nodep->taskp());	// First, do hierarchical funcs
+	UINFO(4," FTask REF   "<<nodep<<endl);
+	if (debug()>=9) { nodep->dumpTree(cout,"-inlfunc:"); }
+	if (!m_scopep) nodep->v3fatalSrc("func ref not under scope");
+	string namePrefix = ((nodep->castFuncRef()?"__Vfunc_":"__Vtask_")
+			     +nodep->taskp()->shortName()+"__"+cvtToStr(m_modNCalls++));
+	// Create output variable
+	AstVarScope* outvscp = NULL;
+	if (nodep->taskp()->isFunction()) {
+	    // Not that it's a FUNCREF, but that we're calling a function (perhaps as a task)
+	    outvscp = createVarScope (nodep->taskp()->fvarp()->castVar(),
+				      namePrefix+"__Vfuncout");
+	}
+	// Create cloned statements
 	AstNode* beginp;
 	if (m_statep->ftaskNoInline(nodep->taskp())) {
 	    // This may share VarScope's with a public task, if any.  Yuk.
@@ -1053,13 +1038,20 @@ private:
 	    beginp = createInlinedFTask(nodep, namePrefix, outvscp);
 	}
 	// Replace the ref
-	AstVarRef* outrefp = new AstVarRef (nodep->fileline(), outvscp, false);
-	nodep->replaceWith(outrefp);
-	// Insert new statements
-	insertBeforeStmt(nodep, beginp);
+	if (nodep->castFuncRef()) {
+	    if (!nodep->taskp()->isFunction()) nodep->v3fatalSrc("func reference to non-function");
+	    AstVarRef* outrefp = new AstVarRef (nodep->fileline(), outvscp, false);
+	    nodep->replaceWith(outrefp);
+	    // Insert new statements
+	    insertBeforeStmt(nodep, beginp);
+	} else {
+	    // outvscp maybe non-NULL if calling a function in a taskref,
+	    // but if so we want to simply ignore the function result
+	    nodep->replaceWith(beginp);
+	}
 	// Cleanup
 	nodep->deleteTree(); nodep=NULL;
-	UINFO(4,"  Func REF Done.\n");
+	UINFO(4,"  FTask REF Done.\n");
     }
     virtual void visit(AstNodeFTask* nodep, AstNUser*) {
 	UINFO(4," Inline   "<<nodep<<endl);

src/V3Undriven.cpp

@@ -170,27 +170,36 @@ public:
 		// thus undriven+unused bits get UNUSED warnings, as they're not as buggy.
 		if (!unusedMatch(nodep)) {
 		    nodep->v3warn(UNUSED, "Signal is not driven, nor used: "<<nodep->prettyName());
+		    nodep->fileline()->modifyWarnOff(V3ErrorCode::UNUSED, true);  // Warn only once
 		}
 	    } else if (allD && !anyU) {
 		if (!unusedMatch(nodep)) {
 		    nodep->v3warn(UNUSED, "Signal is not used: "<<nodep->prettyName());
+		    nodep->fileline()->modifyWarnOff(V3ErrorCode::UNUSED, true);  // Warn only once
 		}
 	    } else if (!anyD && allU) {
 		nodep->v3warn(UNDRIVEN, "Signal is not driven: "<<nodep->prettyName());
+		nodep->fileline()->modifyWarnOff(V3ErrorCode::UNDRIVEN, true);  // Warn only once
 	    } else {
 		// Bits have different dispositions
+		bool setU=false; bool setD=false;
 		if (anynotDU && !unusedMatch(nodep)) {
 		    nodep->v3warn(UNUSED, "Bits of signal are not driven, nor used: "<<nodep->prettyName()
 				  <<bitNames(BN_BOTH));
+		    setU=true;
 		}
 		if (anyDnotU && !unusedMatch(nodep)) {
 		    nodep->v3warn(UNUSED, "Bits of signal are not used: "<<nodep->prettyName()
 				  <<bitNames(BN_UNUSED));
+		    setU=true;
 		}
 		if (anyUnotD) {
 		    nodep->v3warn(UNDRIVEN, "Bits of signal are not driven: "<<nodep->prettyName()
 				  <<bitNames(BN_UNDRIVEN));
+		    setD=true;
 		}
+		if (setU) nodep->fileline()->modifyWarnOff(V3ErrorCode::UNUSED, true);  // Warn only once
+		if (setD) nodep->fileline()->modifyWarnOff(V3ErrorCode::UNDRIVEN, true);  // Warn only once
 	    }
 	}
     }

src/config_build.h.in

@@ -25,7 +25,7 @@
 //**********************************************************************
 //**** Version and host name
 
-#define DTVERSION	"Verilator 3.810 2010/07/10"
+#define DTVERSION	"Verilator 3.811 2011/02/14"
 
 //**********************************************************************
 //**** Functions

src/verilog.y

@@ -151,7 +151,7 @@ const AstBasicDTypeKwd LOGIC_IMPLICIT = AstBasicDTypeKwd::LOGIC_IMPLICIT;
 //======================================================================
 // Macro functions
 
-#define CRELINE() (PARSEP->copyOrSameFileLine())
+#define CRELINE() (PARSEP->copyOrSameFileLine())  // Only use in empty rules, so lines point at beginnings
 
 #define VARRESET_LIST(decl)    { GRAMMARP->m_pinNum=1; VARRESET(); VARDECL(decl); }	// Start of pinlist
 #define VARRESET_NONLIST(decl) { GRAMMARP->m_pinNum=0; VARRESET(); VARDECL(decl); }	// Not in a pinlist
@@ -160,7 +160,7 @@ const AstBasicDTypeKwd LOGIC_IMPLICIT = AstBasicDTypeKwd::LOGIC_IMPLICIT;
 #define VARIO(type) { GRAMMARP->m_varIO = AstVarType::type; }
 #define VARDTYPE(dtypep) { GRAMMARP->setDType(dtypep); }
 
-#define VARDONEA(name,array,attrs) GRAMMARP->createVariable(CRELINE(),(name),(array),(attrs))
+#define VARDONEA(fl,name,array,attrs) GRAMMARP->createVariable((fl),(name),(array),(attrs))
 #define VARDONEP(portp,array,attrs) GRAMMARP->createVariable((portp)->fileline(),(portp)->name(),(array),(attrs))
 #define PINNUMINC() (GRAMMARP->m_pinNum++)
 
@@ -777,10 +777,10 @@ port<nodep>:			// ==IEEE: port
 	//			// IEEE: interface_port_header port_identifier { unpacked_dimension }
 	//			// Expanded interface_port_header
 	//			// We use instantCb here because the non-port form looks just like a module instantiation
-	//UNSUP	portDirNetE id/*interface*/                      idAny/*port*/ rangeListE sigAttrListE	{ VARDTYPE($2); VARDONEA($3, $4); PARSEP->instantCb(CRELINE(), $2, $3, $4); PINNUMINC(); }
-	//UNSUP	portDirNetE yINTERFACE                           idAny/*port*/ rangeListE sigAttrListE	{ VARDTYPE($2); VARDONEA($3, $4); PINNUMINC(); }
-	//UNSUP	portDirNetE id/*interface*/ '.' idAny/*modport*/ idAny/*port*/ rangeListE sigAttrListE	{ VARDTYPE($2); VARDONEA($5, $6); PARSEP->instantCb(CRELINE(), $2, $5, $6); PINNUMINC(); }
-	//UNSUP	portDirNetE yINTERFACE      '.' idAny/*modport*/ idAny/*port*/ rangeListE sigAttrListE	{ VARDTYPE($2); VARDONEA($5, $6); PINNUMINC(); }
+	//UNSUP	portDirNetE id/*interface*/                      idAny/*port*/ rangeListE sigAttrListE	{ VARDTYPE($2); VARDONEA($<fl>3, $3, $4); PARSEP->instantCb($<fl>2, $2, $3, $4); PINNUMINC(); }
+	//UNSUP	portDirNetE yINTERFACE                           idAny/*port*/ rangeListE sigAttrListE	{ VARDTYPE($2); VARDONEA($<fl>3, $3, $4); PINNUMINC(); }
+	//UNSUP	portDirNetE id/*interface*/ '.' idAny/*modport*/ idAny/*port*/ rangeListE sigAttrListE	{ VARDTYPE($2); VARDONEA($<fl>5, $5, $6); PARSEP->instantCb($<fl>2, $2, $5, $6); PINNUMINC(); }
+	//UNSUP	portDirNetE yINTERFACE      '.' idAny/*modport*/ idAny/*port*/ rangeListE sigAttrListE	{ VARDTYPE($2); VARDONEA($<fl>5, $5, $6); PINNUMINC(); }
 	//
 	//			// IEEE: ansi_port_declaration, with [port_direction] removed
 	//			//   IEEE: [ net_port_header | interface_port_header ] port_identifier { unpacked_dimension }
@@ -849,8 +849,8 @@ port_declNetE:			// IEEE: part of port_declaration, optional net type
  	;
  
 portSig<nodep>:
-		id/*port*/				{ $$ = new AstPort(CRELINE(),PINNUMINC(),*$1); }
-	|	idSVKwd					{ $$ = new AstPort(CRELINE(),PINNUMINC(),*$1); }
+		id/*port*/				{ $$ = new AstPort($<fl>1,PINNUMINC(),*$1); }
+	|	idSVKwd					{ $$ = new AstPort($<fl>1,PINNUMINC(),*$1); }
  	;
 
 //**********************************************************************
@@ -926,7 +926,7 @@ list_of_genvar_identifiers<nodep>:	// IEEE: list_of_genvar_identifiers (for decl
 genvar_identifierDecl<nodep>:		// IEEE: genvar_identifier (for declaration)
 		id/*new-genvar_identifier*/ sigAttrListE
 			{ VARRESET_NONLIST(GENVAR); VARDTYPE(new AstBasicDType($<fl>1,AstBasicDTypeKwd::INTEGER));
-			  $$ = VARDONEA(*$1, NULL, $2); }
+			  $$ = VARDONEA($<fl>1, *$1, NULL, $2); }
 	;
 
 local_parameter_declaration<nodep>:	// IEEE: local_parameter_declaration
@@ -1121,9 +1121,9 @@ list_of_variable_decl_assignments<nodep>:	// ==IEEE: list_of_variable_decl_assig
 
 variable_decl_assignment<varp>:	// ==IEEE: variable_decl_assignment
 		id variable_dimensionListE sigAttrListE
-			{ $$ = VARDONEA(*$1,$2,$3); }
+			{ $$ = VARDONEA($<fl>1,*$1,$2,$3); }
 	|	id variable_dimensionListE sigAttrListE '=' variable_declExpr
-			{ $$ = VARDONEA(*$1,$2,$3); $$->valuep($5); }
+			{ $$ = VARDONEA($<fl>1,*$1,$2,$3); $$->valuep($5); }
 	|	idSVKwd					{ $$ = NULL; }
 	//
 	//			// IEEE: "dynamic_array_variable_identifier '[' ']' [ '=' dynamic_array_new ]"
@@ -1144,9 +1144,9 @@ list_of_tf_variable_identifiers<nodep>: // ==IEEE: list_of_tf_variable_identifie
 
 tf_variable_identifier<varp>:		// IEEE: part of list_of_tf_variable_identifiers
 		id variable_dimensionListE sigAttrListE
-			{ $$ = VARDONEA(*$1, $2, $3); }
+			{ $$ = VARDONEA($<fl>1,*$1, $2, $3); }
 	|	id variable_dimensionListE sigAttrListE '=' expr
-			{ $$ = VARDONEA(*$1, $2, $3);
+			{ $$ = VARDONEA($<fl>1,*$1, $2, $3);
 			  $$->addNext(new AstAssign($4, new AstVarRef($4, *$1, true), $5)); }
 	;
 
@@ -1384,7 +1384,7 @@ module_or_generate_item_declaration<nodep>:	// ==IEEE: module_or_generate_item_d
 generate_block_or_null<nodep>:	// IEEE: generate_block_or_null
 	//	';'		// is included in
 	//			// IEEE: generate_block
-		genItem					{ $$ = new AstBegin(CRELINE(),"genblk",$1); }
+		genItem					{ $$ = $1 ? (new AstBegin($1->fileline(),"genblk",$1)) : NULL; }
 	|	genItemBegin				{ $$ = $1; }
 	;
 
@@ -1515,18 +1515,18 @@ netSigList<varp>:		// IEEE: list_of_port_identifiers
 	;
 
 netSig<varp>:			// IEEE: net_decl_assignment -  one element from list_of_port_identifiers
-		netId sigAttrListE			{ $$ = VARDONEA(*$1, NULL, $2); }
-	|	netId sigAttrListE '=' expr		{ $$ = VARDONEA(*$1, NULL, $2); $$->addNext(new AstAssignW($3,new AstVarRef($3,$$->name(),true),$4)); }
-	|	netId rangeList sigAttrListE		{ $$ = VARDONEA(*$1, $2, $3); }
+		netId sigAttrListE			{ $$ = VARDONEA($<fl>1,*$1, NULL, $2); }
+	|	netId sigAttrListE '=' expr		{ $$ = VARDONEA($<fl>1,*$1, NULL, $2); $$->addNext(new AstAssignW($3,new AstVarRef($3,$$->name(),true),$4)); }
+	|	netId rangeList sigAttrListE		{ $$ = VARDONEA($<fl>1,*$1, $2, $3); }
 	;
 
 netId<strp>:
-		id/*new-net*/				{ $$ = $1; }
-	|	idSVKwd					{ $$ = $1; }
+		id/*new-net*/				{ $$ = $1; $<fl>$=$<fl>1; }
+	|	idSVKwd					{ $$ = $1; $<fl>$=$<fl>1; }
 	;
 
 sigId<varp>:
-		id					{ $$ = VARDONEA(*$1, NULL, NULL); }
+		id					{ $$ = VARDONEA($<fl>1,*$1, NULL, NULL); }
 	;
 
 sigAttrListE<nodep>:
@@ -1564,7 +1564,7 @@ rangeList<rangep>:		// IEEE: {packed_dimension}
 
 wirerangeE<dtypep>:
 		/* empty */    		               	{ $$ = new AstBasicDType(CRELINE(), LOGIC); }  // not implicit
-	|	rangeList 				{ $$ = GRAMMARP->addRange(new AstBasicDType(CRELINE(), LOGIC),$1,false); }  // not implicit
+	|	rangeList 				{ $$ = GRAMMARP->addRange(new AstBasicDType($1->fileline(), LOGIC),$1,false); }  // not implicit
 	;
 
 // IEEE: select
@@ -1646,8 +1646,8 @@ instnameList<nodep>:
 	;
 
 instnameParen<nodep>:
-		id instRangeE '(' cellpinList ')'	{ $$ = new AstCell($3,       *$1,GRAMMARP->m_instModule,$4,  GRAMMARP->m_instParamp,$2); }
-	|	id instRangeE 				{ $$ = new AstCell(CRELINE(),*$1,GRAMMARP->m_instModule,NULL,GRAMMARP->m_instParamp,$2); }
+		id instRangeE '(' cellpinList ')'	{ $$ = new AstCell($<fl>1,*$1,GRAMMARP->m_instModule,$4,  GRAMMARP->m_instParamp,$2); }
+	|	id instRangeE 				{ $$ = new AstCell($<fl>1,*$1,GRAMMARP->m_instModule,NULL,GRAMMARP->m_instParamp,$2); }
 	//UNSUP	instRangeE '(' cellpinList ')'		{ UNSUP } // UDP
 	;
 
@@ -1667,11 +1667,12 @@ cellpinItList<pinp>:		// IEEE: list_of_port_connections + list_of_parameter_assi
 	;
 
 cellpinItemE<pinp>:		// IEEE: named_port_connection + named_parameter_assignment + empty
-		/* empty: ',,' is legal */		{ $$ = NULL; PINNUMINC(); }
+				// Note empty can match either () or (,); V3LinkCells cleans up ()
+		/* empty: ',,' is legal */		{ $$ = new AstPin(CRELINE(),PINNUMINC(),"",NULL); }
 	|	yP_DOTSTAR				{ $$ = new AstPin($1,PINNUMINC(),".*",NULL); }
-	|	'.' idSVKwd				{ $$ = NULL; PINNUMINC(); }
+	|	'.' idSVKwd				{ $$ = new AstPin($1,PINNUMINC(),*$2,new AstVarRef($1,*$2,false)); $$->svImplicit(true);}
 	|	'.' idAny				{ $$ = new AstPin($1,PINNUMINC(),*$2,new AstVarRef($1,*$2,false)); $$->svImplicit(true);}
-	|	'.' idAny '(' ')'			{ $$ = NULL; PINNUMINC(); }
+	|	'.' idAny '(' ')'			{ $$ = new AstPin($1,PINNUMINC(),*$2,NULL); }
 	//			// mintypmax is expanded here, as it might be a UDP or gate primitive
 	|	'.' idAny '(' expr ')'			{ $$ = new AstPin($1,PINNUMINC(),*$2,$4); }
 	//UNSUP	'.' idAny '(' expr ':' expr ')'		{ }
@@ -1733,7 +1734,7 @@ senitem<senitemp>:		// IEEE: part of event_expression, non-'OR' ',' terms
 	;
 
 senitemVar<senitemp>:
-		idClassSel				{ $$ = new AstSenItem(CRELINE(),AstEdgeType::ET_ANYEDGE,$1); }
+		idClassSel				{ $$ = new AstSenItem($1->fileline(),AstEdgeType::ET_ANYEDGE,$1); }
 	;
 
 senitemEdge<senitemp>:		// IEEE: part of event_expression
@@ -2008,7 +2009,7 @@ for_initialization<nodep>:	// ==IEEE: for_initialization + for_variable_declarat
 	//			// IEEE: for_variable_declaration
 		varRESET data_type idAny/*new*/ '=' expr ';'
 			{ VARDTYPE($2);
-			  $$ = VARDONEA(*$3,NULL,NULL);
+			  $$ = VARDONEA($<fl>3,*$3,NULL,NULL);
 			  $$->addNext(new AstAssign($4,new AstVarRef($4,*$3,true),$5));}
 	|	varRefBase '=' expr ';'			{ $$ = new AstAssign($2,$1,$3); }
 	//UNSUP: List of initializations
@@ -2032,10 +2033,10 @@ for_step<nodep>:		// IEEE: for_step
 // Functions/tasks
 
 taskRef<ftaskrefp>:		// IEEE: part of tf_call
-		idDotted		 		{ $$ = new AstTaskRef(CRELINE(),new AstParseRef($1->fileline(), AstParseRefExp::PX_TASK, $1),NULL);}
-	|	idDotted '(' list_of_argumentsE ')'	{ $$ = new AstTaskRef(CRELINE(),new AstParseRef($1->fileline(), AstParseRefExp::PX_TASK, $1),$3);}
-	//UNSUP: package_scopeIdFollows idDotted		{ $$ = new AstTaskRef(CRELINE(),new AstParseRef($2->fileline(), AstParseRefExp::PX_TASK, $2),NULL);}
-	//UNSUP: package_scopeIdFollows idDotted '(' list_of_argumentsE ')'	{ $$ = new AstTaskRef(CRELINE(),new AstParseRef($2->fileline(), AstParseRefExp::PX_TASK, $2),$4);}
+		idDotted		 		{ $$ = new AstTaskRef($1->fileline(),new AstParseRef($1->fileline(), AstParseRefExp::PX_TASK, $1),NULL);}
+	|	idDotted '(' list_of_argumentsE ')'	{ $$ = new AstTaskRef($1->fileline(),new AstParseRef($1->fileline(), AstParseRefExp::PX_TASK, $1),$3);}
+	//UNSUP: package_scopeIdFollows idDotted		{ $$ = new AstTaskRef($1->fileline(),new AstParseRef($2->fileline(), AstParseRefExp::PX_TASK, $2),NULL);}
+	//UNSUP: package_scopeIdFollows idDotted '(' list_of_argumentsE ')'	{ $$ = new AstTaskRef($1->fileline(),new AstParseRef($2->fileline(), AstParseRefExp::PX_TASK, $2),$4);}
 	//UNSUP: idDotted is really just id to allow dotted method calls
 	;
 
@@ -2281,9 +2282,9 @@ tf_port_itemDir:		// IEEE: part of tf_port_item, direction
 
 tf_port_itemAssignment<varp>:	// IEEE: part of tf_port_item, which has assignment
 		id variable_dimensionListE sigAttrListE
-			{ $$ = VARDONEA(*$1, $2, $3); }
+			{ $$ = VARDONEA($<fl>1, *$1, $2, $3); }
 	|	id variable_dimensionListE sigAttrListE '=' expr
-			{ $$ = VARDONEA(*$1, $2, $3); $$->valuep($5); }
+			{ $$ = VARDONEA($<fl>1, *$1, $2, $3); $$->valuep($5); }
 	;
 
 parenE:
@@ -2819,8 +2820,8 @@ idAny<strp>:			// Any kind of identifier
 
 idSVKwd<strp>:			// Warn about non-forward compatible Verilog 2001 code
 	//			// yBIT, yBYTE won't work here as causes conflicts
-		yDO					{ static string s = "do"   ; $$ = &s; ERRSVKWD($1,*$$); }
-	|	yFINAL					{ static string s = "final"; $$ = &s; ERRSVKWD($1,*$$); }
+		yDO					{ static string s = "do"   ; $$ = &s; ERRSVKWD($1,*$$); $<fl>$=$<fl>1; }
+	|	yFINAL					{ static string s = "final"; $$ = &s; ERRSVKWD($1,*$$); $<fl>$=$<fl>1; }
 	;
 
 variable_lvalue<nodep>:		// IEEE: variable_lvalue or net_lvalue
@@ -2872,7 +2873,7 @@ idDottedMore<nodep>:
 // id below includes:
 //	 enum_identifier
 idArrayed<nodep>:		// IEEE: id + select
-		id						{ $$ = new AstText(CRELINE(),*$1); }
+		id						{ $$ = new AstText($<fl>1,*$1); }
 	//			// IEEE: id + part_select_range/constant_part_select_range
 	|	idArrayed '[' expr ']'				{ $$ = new AstSelBit($2,$1,$3); }  // Or AstArraySel, don't know yet.
 	|	idArrayed '[' constExpr ':' constExpr ']'	{ $$ = new AstSelExtract($2,$1,$3,$5); }
@@ -2883,7 +2884,7 @@ idArrayed<nodep>:		// IEEE: id + select
 
 // VarRef without any dots or vectorizaion
 varRefBase<varrefp>:
-		id					{ $$ = new AstVarRef(CRELINE(),*$1,false);}
+		id					{ $$ = new AstVarRef($<fl>1,*$1,false);}
 	;
 
 // yaSTRING shouldn't be used directly, instead via an abstraction below
@@ -3091,7 +3092,7 @@ void V3ParseImp::parserClear() {
 AstNode* V3ParseGrammar::createSupplyExpr(FileLine* fileline, string name, int value) {
     FileLine* newfl = new FileLine (fileline);
     newfl->warnOff(V3ErrorCode::WIDTH, true);
-    AstNode* nodep = new AstConst(newfl, V3Number(fileline));
+    AstNode* nodep = new AstConst(newfl, V3Number(newfl));
     // Adding a NOT is less work than figuring out how wide to make it
     if (value) nodep = new AstNot(newfl, nodep);
     nodep = new AstAssignW(newfl, new AstVarRef(fileline, name, true),

test_regress/t/t_EXAMPLE.v

@@ -13,7 +13,7 @@
 // please note it here, otherwise:**
 //
 // This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2010 by Wilson Snyder.
+// without warranty, 2011 by Wilson Snyder.
 
 module t (/*AUTOARG*/
    // Inputs

test_regress/t/t_cdc_async_bad.pl

@@ -12,11 +12,12 @@ compile (
 	 verilator_make_gcc => 0,
 	 fails => 1,
 	 expect=>
-'%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:\d+: Logic in path that feeds async reset, via signal: TOP->v.rst2_bad_n
+'%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:\d+: Logic in path that feeds async reset, via signal: v.rst2_bad_n
 %Warning-CDCRSTLOGIC: Use "/\* verilator lint_off CDCRSTLOGIC \*/" and lint_on around source to disable this message.
 %Warning-CDCRSTLOGIC:      See details in obj_dir/t_cdc_async_bad/Vt_cdc_async_bad__cdc.txt
-%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:\d+: Logic in path that feeds async reset, via signal: TOP->v.rst6a_bad_n
-%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:\d+: Logic in path that feeds async reset, via signal: TOP->v.rst3_bad_n
+%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:\d+: Logic in path that feeds async reset, via signal: v.rst6a_bad_n
+%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:\d+: Logic in path that feeds async reset, via signal: v.rst6b_bad_n
+%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:\d+: Logic in path that feeds async reset, via signal: v.rst3_bad_n
 %Error: Exiting due to.*',
 	 );
 

test_regress/t/t_func.v

@@ -47,6 +47,14 @@ module t;
       nil();
       if (n !== 10) $stop;
 
+      // Functions called as tasks
+      rglobal = 32'h4;
+      if (inc_and_return(32'h2) != 32'h6) $stop;
+      if (rglobal !== 32'h6) $stop;
+      rglobal = 32'h6;
+      inc_and_return(32'h3);
+      if (rglobal !== 32'h9) $stop;
+
       $write("*-* All Finished *-*\n");
       $finish;
    end
@@ -133,4 +141,10 @@ module t;
       toint = fa + 32'h1;
    endfunction
 
+   function [31:0] inc_and_return;
+      input [31:0] inc;
+      rglobal = rglobal + inc;
+      return rglobal;
+   endfunction
+
 endmodule

test_regress/t/t_func_task_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2011 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 v_flags2 => ["--lint-only"],
+	 fails=>1,
+	 expect=>
+q{%Error: t/t_func_task_bad.v:\d+: Illegal call of a task as a function: task_as_func
+%Error: Exiting due to.*},
+	 );
+
+ok(1);
+1;

test_regress/t/t_func_task_bad.v

@@ -0,0 +1,16 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2011 by Wilson Snyder.
+
+module t (/*AUTOARG*/);
+
+   initial begin
+      if (task_as_func(1'b0)) $stop;
+   end
+
+   task task_as_func;
+      input ign;
+   endtask
+
+endmodule

test_regress/t/t_func_tie_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2011 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 v_flags2 => ["--lint-only"],
+	 fails=>1,
+	 expect=>
+q{%Error: t/t_func_tie_bad.v:\d+: Function/task output connected to constant instead of variable: b
+%Error: Exiting due to.*},
+	 );
+
+ok(1);
+1;

test_regress/t/t_func_tie_bad.v

@@ -0,0 +1,19 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2011 by Wilson Snyder.
+
+module t (/*AUTOARG*/);
+
+   initial begin
+      func(0, 1'b1);
+   end
+
+   function automatic int func
+     (
+      input int a,
+      output bit b );
+      return 0;
+   endfunction
+
+endmodule

test_regress/t/t_lint_blksync_loop.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    v_flags2 => ["--lint-only -Wwarn-BLKSEQ -Wwarn-COMBDLY"],
+    fails=>0,
+    verilator_make_gcc => 0,
+    make_top_shell => 0,
+    make_main => 0,
+    ) if $Self->{v3};
+
+ok(1);
+1;

test_regress/t/t_lint_blksync_loop.v

@@ -0,0 +1,102 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2010 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Outputs
+   data_out,
+   // Inputs
+   wr, wa, rst_l, rd, ra, data_in, clk
+   );
+   input clk;
+
+   /*AUTOINPUT*/
+   // Beginning of automatic inputs (from unused autoinst inputs)
+   input [31:0]		data_in;		// To sub of reg_1r1w.v
+   input [7:0]		ra;			// To sub of reg_1r1w.v
+   input		rd;			// To sub of reg_1r1w.v
+   input		rst_l;			// To sub of reg_1r1w.v
+   input [7:0]		wa;			// To sub of reg_1r1w.v
+   input		wr;			// To sub of reg_1r1w.v
+   // End of automatics
+   /*AUTOOUTPUT*/
+   // Beginning of automatic outputs (from unused autoinst outputs)
+   output [31:0]	data_out;		// From sub of reg_1r1w.v
+   // End of automatics
+
+   reg_1r1w #(.WIDTH(32), .DEPTH(256), .ADRWID(8))
+   sub 
+     (/*AUTOINST*/
+      // Outputs
+      .data_out				(data_out[31:0]),
+      // Inputs
+      .data_in				(data_in[31:0]),
+      .ra				(ra[7:0]),
+      .wa				(wa[7:0]),
+      .wr				(wr),
+      .rd				(rd),
+      .clk				(clk),
+      .rst_l				(rst_l));
+
+endmodule
+
+module reg_1r1w
+   #(
+     parameter WIDTH=32,
+     parameter ADRWID=10,
+     parameter DEPTH=1024,
+     parameter RST=0
+     )
+    (/*AUTOARG*/
+   // Outputs
+   data_out,
+   // Inputs
+   data_in, ra, wa, wr, rd, clk, rst_l
+   );
+
+    input [WIDTH-1:0] data_in;
+    input [ADRWID-1:0] ra;
+    input [ADRWID-1:0] wa;
+    input wr;
+    input rd;
+    input clk;
+    input rst_l;
+
+    output [WIDTH-1:0] data_out;
+
+    reg [WIDTH-1:0] array [0:DEPTH-1];
+    reg [ADRWID-1:0] ra_r, wa_r;
+    reg [WIDTH-1:0]  data_in_r;
+    reg             wr_r;
+    reg             rd_r;
+
+    integer        x;
+
+    always @(posedge clk or negedge rst_l) begin
+       if (!rst_l) begin
+	  for (x=0; x<DEPTH; x=x+1) begin // <== VERILATOR FLAGS THIS LINE
+             if (RST == 1) begin
+		array[x] <= 0;
+             end
+	  end
+	  ra_r <= 0;
+	  wa_r <= 0;
+	  wr_r <= 0;
+	  rd_r <= 0;
+	  data_in_r <= 0;
+       end
+       else begin
+	  ra_r <= ra;
+	  wa_r <= wa;
+	  wr_r <= wr;
+	  rd_r <= rd;
+	  data_in_r <= data_in;
+	  if (wr_r) array[wa_r] <= data_in_r;
+       end
+    end
+endmodule
+
+// Local Variables:
+// verilog-auto-inst-param-value: t
+// End:

test_regress/t/t_lint_once_bad.pl

@@ -0,0 +1,24 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 make_top_shell => 0,
+	 make_main => 0,
+	 v_flags2 => ["--lint-only -Wwarn-UNUSED"],
+	 verilator_make_gcc => 0,
+	 fails=>1,
+	 expect=>
+'%Warning-UNUSED: t/t_lint_once_bad.v:\d+: Signal is not driven, nor used: unus1
+%Warning-UNUSED: Use .* to disable this message.
+%Warning-UNUSED: t/t_lint_once_bad.v:\d+: Signal is not driven, nor used: unus2
+%Error: Exiting due to.*',
+	 ) if $Self->{v3};
+
+ok(1);
+1;

test_regress/t/t_lint_once_bad.v

@@ -0,0 +1,19 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2006 by Wilson Snyder.
+
+// Check that we report warnings only once on parameterized modules
+// Also check that we don't suppress warnings on the same line
+
+module t ();
+   sub #(.A(1)) sub1();
+   sub #(.A(2)) sub2();
+   sub #(.A(3)) sub3();
+endmodule
+
+module sub;
+   parameter A = 0;
+
+   reg [A:0] unus1;    reg [A:0] unus2;
+endmodule

test_regress/t/t_lint_pindup_bad.pl

@@ -0,0 +1,28 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    v_flags2 => ["--lint-only"],
+    fails=>1,
+    verilator_make_gcc => 0,
+    make_top_shell => 0,
+    make_main => 0,
+    expect=>
+'%Error: t/t_lint_pindup_bad.v:\d+: Duplicate pin connection: i
+%Error: t/t_lint_pindup_bad.v:\d+: ... Location of original pin connection
+%Error: t/t_lint_pindup_bad.v:\d+: Pin not found: __pinNumber4
+%Error: t/t_lint_pindup_bad.v:\d+: Duplicate pin connection: P
+%Error: t/t_lint_pindup_bad.v:\d+: ... Location of original pin connection
+%Error: t/t_lint_pindup_bad.v:\d+: Duplicate pin connection: P
+%Error: t/t_lint_pindup_bad.v:\d+: ... Location of original pin connection
+%Error: Exiting due to.*',
+    ) if $Self->{v3};
+
+ok(1);
+1;

test_regress/t/t_lint_pindup_bad.v

@@ -0,0 +1,31 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2010 by Wilson Snyder.
+
+module t
+   (
+   output wire o,
+   input wire i,
+   input wire i2
+   );
+
+   sub
+     #(, .P(2), .P(3))
+   sub (.o(o),
+	.i(i),
+	.i(i2),
+	);
+
+endmodule
+
+module sub
+  #(parameter P=1)
+  (
+   output wire o,
+   input wire i
+   );
+
+   assign o = ~i;
+
+endmodule

test_regress/t/t_lint_setout_bad.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    v_flags2 => ["--lint-only"],
+    fails=>1,
+    verilator_make_gcc => 0,
+    make_top_shell => 0,
+    make_main => 0,
+    expect=>
+'%Error: t/t_lint_setout_bad.v:\d+: Output port is connected to a constant pin, electrical short
+.*',
+    ) if $Self->{v3};
+
+ok(1);
+1;

test_regress/t/t_lint_setout_bad.v

@@ -0,0 +1,34 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2011 by Wilson Snyder.
+
+module t
+  (
+   input wire reset_l,
+   input wire clk
+   );
+
+   sub sub_I
+     (
+      .clk(clk),
+      .reset_l(reset_l),
+      .cpu_if_timeout(1'b0)
+      );
+endmodule
+
+module sub
+  (
+   input wire	clk, reset_l,
+   output reg	cpu_if_timeout
+   );
+
+   always @(posedge clk) begin
+      if (!reset_l) begin
+	 cpu_if_timeout <= 1'b0;
+      end
+      else begin
+	 cpu_if_timeout <= 1'b0;
+      end
+   end
+endmodule

test_regress/t/t_lint_setout_bad_noinl.pl

@@ -0,0 +1,24 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+top_filename("t/t_lint_setout_bad.v");
+
+compile (
+    v_flags2 => ["--lint-only -Oi"],
+    fails=>1,
+    verilator_make_gcc => 0,
+    make_top_shell => 0,
+    make_main => 0,
+    expect=>
+'%Error: t/t_lint_setout_bad.v:\d+: Output port is connected to a constant pin, electrical short
+.*',
+    ) if $Self->{v3};
+
+ok(1);
+1;

test_regress/t/t_lint_syncasyncnet_bad.pl

@@ -14,7 +14,7 @@ compile (
     make_top_shell => 0,
     make_main => 0,
     expect=>
-'%Warning-SYNCASYNCNET: t/t_lint_syncasyncnet_bad.v:\d+: Signal flopped as both synchronous and async: TOP->rst_both_l
+'%Warning-SYNCASYNCNET: t/t_lint_syncasyncnet_bad.v:\d+: Signal flopped as both synchronous and async: rst_both_l
 %Warning-SYNCASYNCNET: Use .* around source to disable this message.
 %Warning-SYNCASYNCNET: t/t_lint_syncasyncnet_bad.v:\d+: ... Location of async usage
 %Warning-SYNCASYNCNET: t/t_lint_syncasyncnet_bad.v:\d+: ... Location of sync usage

test_regress/t/t_pipe_filter.out

@@ -1,11 +1,13 @@
 `line 1 "t/t_pipe_filter.v" 1
+ 
 
+`line 3 "t/t_pipe_filter.v" 0
+ 
+ 
 
-
-
-
-
-
+`line 6 "t/t_pipe_filter.v" 0
+ 
+ 
 
 
 `line 10 "t/t_pipe_filter.v" 0
@@ -19,37 +21,39 @@ example line 11;
 int lint_off_line_7 = 1;
 `line 2 "t/t_pipe_filter_inc.vh" 0
 int lint_off_line_8 = 1;
+ 
 
-
-
-
+`line 5 "t/t_pipe_filter_inc.vh" 0
+ 
+ 
 
 `line 8 "t/t_pipe_filter_inc.vh" 0
 inc line 6;
-inc line 7;  
-inc line 8;  
+inc line 7;   
+inc line 8;   
 inc line 9;
 
 `line 13 "t/t_pipe_filter_inc.vh" 2
 `line 13 "t/t_pipe_filter.v" 0
 
-
-`line 15 "t/t_pipe_filter.v" 0
+`line 14 "t/t_pipe_filter.v" 0
+ 
  
 `line 15 "t/t_pipe_filter.v" 0
 `line 1 "t/t_pipe_filter_inc.vh" 1
 int lint_off_line_7 = 1;
 `line 2 "t/t_pipe_filter_inc.vh" 0
 int lint_off_line_8 = 1;
+ 
 
-
-
-
+`line 5 "t/t_pipe_filter_inc.vh" 0
+ 
+ 
 
 `line 8 "t/t_pipe_filter_inc.vh" 0
 inc line 6;
-inc line 7;  
-inc line 8;  
+inc line 7;   
+inc line 8;   
 inc line 9;
 
 `line 13 "t/t_pipe_filter_inc.vh" 2

test_regress/t/t_preproc.out

@@ -1,39 +1,38 @@
 `line 1 "t/t_preproc.v" 1
+ 
+ 
+ 
 
-
-
-
-
-
-`line 7 "t/t_preproc.v" 0
+`line 5 "t/t_preproc.v" 0
+ 
+ 
  
 `line 7 "t/t_preproc.v" 0
 `line 1 "t/t_preproc_inc2.vh" 1
-
-`line 3 "t/t_preproc_inc2.vh" 0
-
-
-`line 4 "t/t_preproc_inc2.vh" 0
+ 
+`line 2 "t/t_preproc_inc2.vh" 0
+ 
+ 
 At file "t/t_preproc_inc2.vh"  line 4
  
  
 `line 6 "t/t_preproc_inc2.vh" 0
 `line 1 "t/t_preproc_inc3.vh" 1
 `line 2 "inc3_a_filename_from_line_directive" 0
-
-
-
+ 
+ 
+ 
 
 `line 6 "inc3_a_filename_from_line_directive" 0
  
   
   
-  
+   
   At file "inc3_a_filename_from_line_directive"  line 10
 
 `line 12 "inc3_a_filename_from_line_directive" 0
    
- 
+  
 
 `line 15 "inc3_a_filename_from_line_directive" 0
  
@@ -48,23 +47,24 @@ At file "t/t_preproc_inc2.vh"  line 4
 `line 7 "t/t_preproc.v" 0
 
 
-
-
+`line 9 "t/t_preproc.v" 0
+ 
+ 
 
 `line 12 "t/t_preproc.v" 0
-/*verilator pass_thru comment*/
+/*verilator pass_thru comment*/ 
 
 `line 14 "t/t_preproc.v" 0
-/*verilator pass_thru_comment2*/
-
-
+/*verilator pass_thru_comment2*/ 
 
+`line 16 "t/t_preproc.v" 0
+ 
+ 
 
 `line 19 "t/t_preproc.v" 0
  
  
-
-`line 22 "t/t_preproc.v" 0
+ 
    wire [3:0] q = {
 		     1'b1    ,
 		       1'b0  ,
@@ -78,7 +78,7 @@ text.
 `line 31 "t/t_preproc.v" 0
  
  
-foo  bar   
+foo   bar    
 foobar2
 
 `line 36 "t/t_preproc.v" 0
@@ -92,8 +92,8 @@ foobar2
 
 
 
-
-`line 46 "t/t_preproc.v" 0
+`line 45 "t/t_preproc.v" 0
+ 
 first part 
 `line 46 "t/t_preproc.v" 0
   		second part 
@@ -108,7 +108,8 @@ first part
 		       c}
 Line_Preproc_Check 48
 
-
+`line 50 "t/t_preproc.v" 0
+ 
 
 `line 52 "t/t_preproc.v" 0
  
@@ -160,11 +161,13 @@ bar_suffix  more
 `line 86 "t/t_preproc.v" 0
 	$c("Zap(\"","bug2","\");");;
 
+`line 88 "t/t_preproc.v" 0
+ 
+ 
 
-
-
-
-
+`line 91 "t/t_preproc.v" 0
+ 
+ 
 
 `line 94 "t/t_preproc.v" 0
  
@@ -174,7 +177,7 @@ bar_suffix  more
  
  
    initial begin
-      
+       
       $display("pre thrupre thrumid thrupost post: \"right side\"");
       $display("left side: \"right side\"");
       $display("left side: \"right side\"");
@@ -182,25 +185,26 @@ bar_suffix  more
       $display("na: \"right_side\"");
       $display("prep ( midp1 left_side midp2 ( outp ) ): \"right_side\"");
       $display("na: \"nana\"");
-      $display("left_side right_side: \"left_side right_side\"");   
-      $display(": \"\"");  
+      $display("left_side right_side: \"left_side right_side\"");    
+      $display(": \"\"");   
       $display("left side: \"right side\"");
       $display("left side: \"right side\"");
       $display("standalone");
 
 `line 115 "t/t_preproc.v" 0
-      
+       
  
 
       $display("twoline: \"first        second\"");
-      
+       
       $write("*-* All Finished *-*\n");
       $finish;
    end
 endmodule
 
-
-
+`line 125 "t/t_preproc.v" 0
+ 
+ 
 
 `line 128 "t/t_preproc.v" 0
  
@@ -216,7 +220,7 @@ wire  tmp_d1 = d1;
 `line 134 "t/t_preproc.v" 0
 wire  tmp_o1 = tmp_d1 + 1; 
 `line 134 "t/t_preproc.v" 0
-assign o1 = tmp_o1 ;   
+assign o1 = tmp_o1 ;    
 endmodule
 module add2 ( input wire d2, output wire o2);
  
@@ -225,7 +229,7 @@ wire  tmp_d2 = d2;
 `line 137 "t/t_preproc.v" 0
 wire  tmp_o2 = tmp_d2 + 1; 
 `line 137 "t/t_preproc.v" 0
-assign o2 = tmp_o2 ;  
+assign o2 = tmp_o2 ;   
 endmodule
 
 `line 140 "t/t_preproc.v" 0
@@ -235,8 +239,8 @@ endmodule
 
 
 
-
-`line 147 "t/t_preproc.v" 0
+`line 146 "t/t_preproc.v" 0
+ 
   
   
   
@@ -250,11 +254,11 @@ endmodule
 `line 151 "t/t_preproc.v" 0
       psl cover { ~m5k.f .ctl._ctl_mvldx_m1.d[i] &  m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1"; 
 `line 151 "t/t_preproc.v" 0
-   end endgenerate	
+   end endgenerate	 
 
-
-
-`line 155 "t/t_preproc.v" 0
+`line 153 "t/t_preproc.v" 0
+ 
+ 
 module prot();
 `protected
     I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl)
@@ -262,11 +266,11 @@ module prot();
 `endprotected
 `line 160 "t/t_preproc.v" 0
 endmodule
+ 
 
-
-
-
-`line 165 "t/t_preproc.v" 0
+`line 163 "t/t_preproc.v" 0
+ 
+ 
  
  
  
@@ -280,17 +284,17 @@ begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs
 begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end
 begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end  more
 
-
-
-`line 179 "t/t_preproc.v" 0
+`line 177 "t/t_preproc.v" 0
+ 
+ 
  
  
 `line 180 "t/t_preproc.v" 0
 `line 1 "t/t_preproc_inc4.vh" 1
-
-`line 3 "t/t_preproc_inc4.vh" 0
-
-
+ 
+`line 2 "t/t_preproc_inc4.vh" 0
+ 
+ 
 
 `line 5 "t/t_preproc_inc4.vh" 0
  
@@ -310,8 +314,9 @@ begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end  more
   
 
 
-
-
+`line 190 "t/t_preproc.v" 0
+ 
+ 
 
 `line 193 "t/t_preproc.v" 0
  
@@ -320,16 +325,18 @@ $blah(this.logfile,vec);
 $blah(this.logfile,vec[1,2,3]);
 $blah(this.logfile,{blah.name(), " is not foo"});
 
-
-
+`line 199 "t/t_preproc.v" 0
+ 
+ 
 
 `line 202 "t/t_preproc.v" 0
 `pragma foo = 1
 `default_nettype none
 `default_nettype uwire
 
-
-
+`line 206 "t/t_preproc.v" 0
+ 
+ 
 
 `line 209 "t/t_preproc.v" 0
  
@@ -339,11 +346,12 @@ $blah(this.logfile,{blah.name(), " is not foo"});
 `line 213 "t/t_preproc.v" 0
 Line_Preproc_Check 213
 
-
-
+`line 215 "t/t_preproc.v" 0
+ 
+ 
 
 `line 218 "t/t_preproc.v" 0
- 
+    
 
 
 (p,q)
@@ -354,21 +362,22 @@ Line_Preproc_Check 213
 (x,y)
 Line_Preproc_Check 226
 
-
-
+`line 228 "t/t_preproc.v" 0
+ 
+ 
 
 `line 231 "t/t_preproc.v" 0
  
  
  
  
-beginend   
 beginend    
-"beginend"  
+beginend     
+"beginend"   
 
-
-
-`line 241 "t/t_preproc.v" 0
+`line 239 "t/t_preproc.v" 0
+ 
+ 
  
  
   `\esc`def
@@ -376,24 +385,24 @@ beginend
 `line 245 "t/t_preproc.v" 0
 Not a \`define
 
-
-
-`line 249 "t/t_preproc.v" 0
+`line 247 "t/t_preproc.v" 0
+ 
+ 
  
  
  
  
 x,y)--bee  submacro has comma paren
 
-
-
-`line 257 "t/t_preproc.v" 0
+`line 255 "t/t_preproc.v" 0
+ 
+ 
  
 $display("bits %d %d", $bits(foo), `10);
 
-
-
-`line 262 "t/t_preproc.v" 0
+`line 260 "t/t_preproc.v" 0
+ 
+ 
  
     
 
@@ -401,9 +410,9 @@ $display("bits %d %d", $bits(foo), `10);
     
     
 
-
-
-`line 270 "t/t_preproc.v" 0
+`line 268 "t/t_preproc.v" 0
+ 
+ 
  
 
 
@@ -441,7 +450,8 @@ $display("bits %d %d", $bits(foo), `10);
 
 `line 284 "t/t_preproc.v" 0
  
-	\
+ 	\
+ 
  
 
 
@@ -449,17 +459,16 @@ $display("bits %d %d", $bits(foo), `10);
 
 
 
-`line 293 "t/t_preproc.v" 0
-
 `line 293 "t/t_preproc.v" 0
    
 `line 293 "t/t_preproc.v" 0
-		
+ 		
 `line 293 "t/t_preproc.v" 0
    def i		
 
 
-
+`line 295 "t/t_preproc.v" 0
+ 
 
 `line 297 "t/t_preproc.v" 0
  
@@ -475,17 +484,17 @@ $display("bits %d %d", $bits(foo), `10);
 
 
 `line 307 "t/t_preproc.v" 0
-1 /*verilator NOT IN DEFINE*/ (nodef)
-2 /*verilator PART OF DEFINE*/ (hasdef)
+1 /*verilator NOT IN DEFINE*/  (nodef)
+2 /*verilator PART OF DEFINE*/  (hasdef)
 3 
 `line 309 "t/t_preproc.v" 0
 /*verilator NOT PART
- OF DEFINE*/ (nodef)
+ OF DEFINE*/  (nodef)
 `line 310 "t/t_preproc.v" 0
 4 
 `line 310 "t/t_preproc.v" 0
 /*verilator PART 
- OF DEFINE*/ (nodef)
+ OF DEFINE*/  (nodef)
 `line 311 "t/t_preproc.v" 0
 5 also in  
 `line 311 "t/t_preproc.v" 0
@@ -496,7 +505,8 @@ HAS a NEW
 `line 314 "t/t_preproc.v" 0
 LINE
 
-
+`line 316 "t/t_preproc.v" 0
+ 
 
 `line 318 "t/t_preproc.v" 0
  
@@ -527,7 +537,7 @@ EXP: do if (start("verilog/inc1.v", 25)) begin  message({"Blah-", "clx_scen", "
 `line 340 "t/t_preproc.v" 0
    do 
 `line 340 "t/t_preproc.v" 0
-       
+        
 `line 340 "t/t_preproc.v" 0
   
 `line 340 "t/t_preproc.v" 0
@@ -543,11 +553,12 @@ EXP: do if (start("verilog/inc1.v", 25)) begin  message({"Blah-", "clx_scen", "
 `line 340 "t/t_preproc.v" 0
       end 
 `line 340 "t/t_preproc.v" 0
-       
+        
 `line 340 "t/t_preproc.v" 0
    while(0);
 
-
+`line 342 "t/t_preproc.v" 0
+ 
 
 `line 344 "t/t_preproc.v" 0
  
@@ -562,21 +573,19 @@ EXP: do if (start("verilog/inc1.v", 25)) begin  message({"Blah-", "clx_scen", "
 
 `line 349 "t/t_preproc.v" 0
      
-
-`line 351 "t/t_preproc.v" 0
+ 
 EXP: This is fooed
 This is fooed
 EXP: This is fooed_2
 This is fooed_2
 
-
-`line 357 "t/t_preproc.v" 0
+`line 356 "t/t_preproc.v" 0
+ 
  
 np
 np
-
-
-`line 362 "t/t_preproc.v" 0
+ 
+ 
  
  
  
@@ -586,9 +595,9 @@ np
  
     
 
-
-
-`line 372 "t/t_preproc.v" 0
+`line 370 "t/t_preproc.v" 0
+ 
+ 
  
  
  
@@ -603,18 +612,17 @@ np
 `line 382 "t/t_preproc.v" 0
 hello3hello3hello3
 hello4hello4hello4hello4
-
-
-`line 386 "t/t_preproc.v" 0
+ 
+ 
  
  
  
 `line 388 "t/t_preproc.v" 0
 `line 1 "t/t_preproc_inc4.vh" 1
-
-`line 3 "t/t_preproc_inc4.vh" 0
-
-
+ 
+`line 2 "t/t_preproc_inc4.vh" 0
+ 
+ 
 
 `line 5 "t/t_preproc_inc4.vh" 0
  
@@ -624,10 +632,9 @@ hello4hello4hello4hello4
 
 `line 389 "t/t_preproc.v" 0
    
-
-
-
-`line 393 "t/t_preproc.v" 0
+ 
+ 
+ 
  
 
  
@@ -639,9 +646,8 @@ hello4hello4hello4hello4
      
      
 Line_Preproc_Check 401
-
-
-`line 404 "t/t_preproc.v" 0
+ 
+ 
  
 
  
@@ -652,15 +658,14 @@ Line_Preproc_Check 407
   BAR "
 `line 410 "t/t_preproc.v" 0
 Line_Preproc_Check 410
-
-
+ 
+ 
 
 `line 414 "t/t_preproc.v" 0
  
  
  
-
-`line 418 "t/t_preproc.v" 0
+ 
  
 abc
  
@@ -679,15 +684,14 @@ sonet_frame
  
 EXP: sonet_frame
 sonet_frame
-
-`line 435 "t/t_preproc.v" 0
+ 
  
  
 EXP: sonet_frame
 sonet_frame
 
-
-`line 441 "t/t_preproc.v" 0
+`line 440 "t/t_preproc.v" 0
+ 
  
  
 EXP: module zzz ; endmodule
@@ -700,6 +704,10 @@ EXP: module a_b ; endmodule
 module a_b ; endmodule
 module a_b ; endmodule
 
+`line 452 "t/t_preproc.v" 0
+ 
+ 
+integer foo;
+ 
 
-
-`line 454 "t/t_preproc.v" 2
+`line 457 "t/t_preproc.v" 2

test_regress/t/t_preproc.v

@@ -450,3 +450,6 @@ module `Q1 ; endmodule
 module `Q1 ; endmodule
 
 //======================================================================
+// bug311
+integer/*NEED_SPACE*/foo;
+//======================================================================

test_regress/t/t_preproc_def09.out

@@ -1,14 +1,15 @@
 `line 1 "t/t_preproc_def09.v" 1
+ 
+
+`line 3 "t/t_preproc_def09.v" 0
+ 
+ 
 
 
 
-
-
-
-
-
-
-`line 10 "t/t_preproc_def09.v" 0
+`line 8 "t/t_preproc_def09.v" 0
+ 
+ 
  
 'initial $display("start", "msg1" , "msg2", "end");'
 'initial $display("start", "msg1"  , "msg2" , "end");'
@@ -20,12 +21,12 @@
 'initial $display("start",  , , "end");'
 'initial $display("start",  , , "end");'
 'initial $display("start",  , , "end");'
+ 
+ 
+ 
 
-
-
-
-
-`line 26 "t/t_preproc_def09.v" 0
+`line 25 "t/t_preproc_def09.v" 0
+ 
  
 '$display(5,,2,,3);'
 '$display(5,,2,,3);'
@@ -33,7 +34,7 @@
 '$display(1 ,,"B",,3 );'
 '$display(5,,2,,);'
 '$display(5,,2,,);'
-
+ 
 
 `line 35 "t/t_preproc_def09.v" 0
  
@@ -50,21 +51,21 @@
 '$display(1 ,,0,,"C");'
 '$display(5,,0,,"C");'
 '$display(5,,0,,"C");'
-
+ 
 
 `line 50 "t/t_preproc_def09.v" 0
  
 'b + 1 + 42 + a'
 'b + 1 + 42 + a'
 
-
-`line 55 "t/t_preproc_def09.v" 0
+`line 54 "t/t_preproc_def09.v" 0
+ 
  
 '"==)" "((((" () ';
 '"==)" "((((" () ';
 
-
-`line 60 "t/t_preproc_def09.v" 0
+`line 59 "t/t_preproc_def09.v" 0
+ 
  
 
 
@@ -79,6 +80,7 @@
 '(6) (eq=al) ZOT'
 HERE-71 - Line71
 
-
+`line 73 "t/t_preproc_def09.v" 0
+ 
 
 `line 75 "t/t_preproc_def09.v" 2

test_regress/t/t_preproc_psl_off.out

@@ -1,29 +1,29 @@
 `line 1 "t/t_preproc_psl.v" 1
+ 
 
 
-
-
-
+`line 4 "t/t_preproc_psl.v" 0
+ 
+ 
 
 `line 7 "t/t_preproc_psl.v" 0
-/*verilator metacomment preserved*/
-
-`line 9 "t/t_preproc_psl.v" 0
-/*verilator metacomment also_preserved*/
+/*verilator metacomment preserved*/ 
+ 
+/*verilator metacomment also_preserved*/ 
 
 `line 11 "t/t_preproc_psl.v" 0
 Hello in t_preproc_psl.v
-   
-   
-   
-   
+    
+    
+    
+    
 
 `line 17 "t/t_preproc_psl.v" 0
-   
-   
-   
-   
-   
+    
+    
+    
+    
+    
    
 
 `line 28 "t/t_preproc_psl.v" 0
@@ -34,13 +34,13 @@ Hello in t_preproc_psl.v
 
 `line 28 "t/t_preproc_psl.v" 0
 
-
-`line 29 "t/t_preproc_psl.v" 0
+`line 28 "t/t_preproc_psl.v" 0
+ 
  29
 
 `line 31 "t/t_preproc_psl.v" 0
-   
-   
+    
+    
    
 
 `line 40 "t/t_preproc_psl.v" 0
@@ -53,36 +53,37 @@ Hello in t_preproc_psl.v
 
 `line 40 "t/t_preproc_psl.v" 0
 
-
-`line 41 "t/t_preproc_psl.v" 0
+`line 40 "t/t_preproc_psl.v" 0
+ 
  41
 
 `line 43 "t/t_preproc_psl.v" 0
-   
+    
 
 `line 45 "t/t_preproc_psl.v" 0
-   
-   
-   
-
-
-`line 50 "t/t_preproc_psl.v" 0
-   
-   
-   
-   
+    
+    
+    
 
+`line 49 "t/t_preproc_psl.v" 0
+ 
+    
+    
+    
+    
 
+`line 55 "t/t_preproc_psl.v" 0
+ 
 
 `line 57 "t/t_preproc_psl.v" 0
  
    
 
 
-
-`line 62 "t/t_preproc_psl.v" 0
+`line 61 "t/t_preproc_psl.v" 0
  
-   
+ 
+    
 
 `line 65 "t/t_preproc_psl.v" 0
  
@@ -91,8 +92,8 @@ psl assert always sig!=90;
   `verilog
 
 
-
-`line 72 "t/t_preproc_psl.v" 0
+`line 71 "t/t_preproc_psl.v" 0
+ 
 72
 
 `line 74 "t/t_preproc_psl.v" 2

test_regress/t/t_preproc_psl_on.out

@@ -1,22 +1,22 @@
 `line 1 "t/t_preproc_psl.v" 1
+ 
 
 
-
-
-
+`line 4 "t/t_preproc_psl.v" 0
+ 
+ 
 
 `line 7 "t/t_preproc_psl.v" 0
-/*verilator metacomment preserved*/
-
-`line 9 "t/t_preproc_psl.v" 0
-/*verilator metacomment also_preserved*/
+/*verilator metacomment preserved*/ 
+ 
+/*verilator metacomment also_preserved*/ 
 
 `line 11 "t/t_preproc_psl.v" 0
 Hello in t_preproc_psl.v
-   
-   
-   
-   
+    
+    
+    
+    
 
 `line 17 "t/t_preproc_psl.v" 0
     psl  default clock = (posedge clk);
@@ -24,27 +24,26 @@ Hello in t_preproc_psl.v
     psl  assert always cyc!=10;
     psl  assert always cyc==3 -> mask==8'h2;
     psl  failsx: cover {cyc==3 && mask==8'h1};
-    psl  fails2:
+     psl  fails2:
         cover {
 	    cyc==3 && mask==8'h9};
-        
+         
 	fails3: always assert {
 	    cyc==3 && mask==8'h10 };
-    
+     
  29
 
 `line 31 "t/t_preproc_psl.v" 0
+    
+    
    
-   
-   
- psl 
-`line 35 "t/t_preproc_psl.v" 0
+  psl 
       fails_ml:
         assert always
   	    cyc==3 -> mask==8'h21;
     psl
       fails_mlalso:  assert always cyc==3 -> mask==8'h21;
-    
+     
  41
 
 `line 43 "t/t_preproc_psl.v" 0
@@ -53,24 +52,25 @@ Hello in t_preproc_psl.v
 `line 45 "t/t_preproc_psl.v" 0
     psl  fails3: assert always
     psl 	    cyc==3 -> mask==8'h21;
-   
+    
 
-
-`line 50 "t/t_preproc_psl.v" 0
+`line 49 "t/t_preproc_psl.v" 0
+ 
     psl  assert always
     psl        {[*]; cyc==3;
     psl         cyc==4; cyc==6};
-   
-
+    
 
+`line 55 "t/t_preproc_psl.v" 0
+ 
 
 `line 57 "t/t_preproc_psl.v" 0
  
       
 
 
-
-`line 62 "t/t_preproc_psl.v" 0
+`line 61 "t/t_preproc_psl.v" 0
+ 
  
     psl  assert always cyc!=10;
 
@@ -81,8 +81,8 @@ psl assert always sig!=90;
   `verilog
 
 
-
-`line 72 "t/t_preproc_psl.v" 0
+`line 71 "t/t_preproc_psl.v" 0
+ 
 72
 
 `line 74 "t/t_preproc_psl.v" 2

test_regress/t/t_tri_dangle.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_tri_dangle.v

@@ -0,0 +1,31 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2011 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inouts
+   AVDD, AVSS
+   );
+   inout AVDD;
+   inout  AVSS;
+
+   sub sub (/*AUTOINST*/
+	    // Inouts
+	    .AVDD			(AVDD),
+	    .AVSS			(AVSS));
+
+   initial begin
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+   end
+endmodule
+
+module sub (/*AUTOARG*/
+   // Inouts
+   AVDD, AVSS
+   );
+   // verilator no_inline_module
+   inout AVDD;
+   inout AVSS;
+endmodule

test_regress/t/t_unopt_combo_bad.pl

@@ -12,13 +12,13 @@ top_filename("t/t_unopt_combo.v");
 compile (
 	 fails=>$Self->{v3},
 	 expect=>
-'%Warning-UNOPTFLAT: t/t_unopt_combo.v:\d+: Signal unoptimizable: Feedback to clock or circular logic: TOP->v.c
+'%Warning-UNOPTFLAT: t/t_unopt_combo.v:\d+: Signal unoptimizable: Feedback to clock or circular logic: v.c
 %Warning-UNOPTFLAT: Use "/\* verilator lint_off UNOPTFLAT \*/" and lint_on around source to disable this message.
-%Warning-UNOPTFLAT:      Example path: t/t_unopt_combo.v:\d+:  TOP->v.c
+%Warning-UNOPTFLAT:      Example path: t/t_unopt_combo.v:\d+:  v.c
 %Warning-UNOPTFLAT:      Example path: t/t_unopt_combo.v:\d+:  ALWAYS
-%Warning-UNOPTFLAT:      Example path: t/t_unopt_combo.v:\d+:  TOP->v.b
+%Warning-UNOPTFLAT:      Example path: t/t_unopt_combo.v:\d+:  v.b
 %Warning-UNOPTFLAT:      Example path: t/t_unopt_combo.v:\d+:  ALWAYS
-%Warning-UNOPTFLAT:      Example path: t/t_unopt_combo.v:\d+:  TOP->v.c
+%Warning-UNOPTFLAT:      Example path: t/t_unopt_combo.v:\d+:  v.c
 %Error: Exiting due to '
 	 );
 

test_regress/t/t_unopt_converge_unopt_bad.pl

@@ -11,7 +11,7 @@ top_filename("t/t_unopt_converge.v");
 
 compile (
 	 fails=>1,
-	 expect=> '%Warning-UNOPT: t/t_unopt_converge.v:\d+: Signal unoptimizable: Feedback to public clock or circular logic: TOP->x
+	 expect=> '%Warning-UNOPT: t/t_unopt_converge.v:\d+: Signal unoptimizable: Feedback to public clock or circular logic: x
 .*
 %Error: Exiting due to '
      ) if $Self->{v3};