Fix error on constants connected to outputs, bug323.

Changes

@@ -15,6 +15,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Fix warnings to point to lowest net usage, not upper level ports.
 
+**** Fix error on constants connected to outputs, bug323.  [Christian Leber]
+
 * Verilator 3.810 2011/01/03
 
 **   Add limited support for VPI access to public signals, see docs.

src/V3Inline.cpp

@@ -140,6 +140,10 @@ private:
 		if (!connectRefp->castConst() && !connectRefp->castVarRef()) {
 		    pinp->v3fatalSrc("Unknown interconnect type; pinReconnectSimple should have cleared up\n");
 		}
+		if (pinNewVarp->isOutOnly() && connectRefp->castConst()) {
+		    pinp->v3error("Output port is connected to a constant pin, electrical short");
+		}
+
 		// Propagate any attributes across the interconnect
 		pinNewVarp->propagateAttrFrom(pinOldVarp);
 		if (connectRefp->castVarRef()) {

test_regress/t/t_lint_setout_bad.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    v_flags2 => ["--lint-only"],
+    fails=>1,
+    verilator_make_gcc => 0,
+    make_top_shell => 0,
+    make_main => 0,
+    expect=>
+'%Error: t/t_lint_setout_bad.v:\d+: Output port is connected to a constant pin, electrical short
+.*',
+    ) if $Self->{v3};
+
+ok(1);
+1;

test_regress/t/t_lint_setout_bad.v

@@ -0,0 +1,34 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2011 by Wilson Snyder.
+
+module t
+  (
+   input wire reset_l,
+   input wire clk
+   );
+
+   sub sub_I
+     (
+      .clk(clk),
+      .reset_l(reset_l),
+      .cpu_if_timeout(1'b0)
+      );
+endmodule
+
+module sub
+  (
+   input wire	clk, reset_l,
+   output reg	cpu_if_timeout
+   );
+
+   always @(posedge clk) begin
+      if (!reset_l) begin
+	 cpu_if_timeout <= 1'b0;
+      end
+      else begin
+	 cpu_if_timeout <= 1'b0;
+      end
+   end
+endmodule

test_regress/t/t_lint_setout_bad_noinl.pl

@@ -0,0 +1,24 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+top_filename("t/t_lint_setout_bad.v");
+
+compile (
+    v_flags2 => ["--lint-only -Oi"],
+    fails=>1,
+    verilator_make_gcc => 0,
+    make_top_shell => 0,
+    make_main => 0,
+    expect=>
+'%Error: t/t_lint_setout_bad.v:\d+: Output port is connected to a constant pin, electrical short
+.*',
+    ) if $Self->{v3};
+
+ok(1);
+1;