1f67080a1f
Tests: Verilog format
2026-03-09 21:39:16 -04:00
7c6c6a684b
Add SPDX copyright identifiers, and get 'reuse' clean. No functional change.
2026-01-26 20:24:34 -05:00
eaf09ba0e7
Dfg: resolve multi-driven signal ranges
...
In order to avoid unexpected breakage on multi-driven variables, we
resolve in DFG construction by using only the first driver encountered.
Also issues the MULTIDRIVEN error for these signals.
2022-11-12 20:34:51 +00:00
1ce360ed5b
Add SPDX license identifiers. No functional change.
2020-03-21 11:24:24 -04:00
50fb7fc8b4
Tests: Resolve self assignment in t_unoptflat_simple_2, Closes #2149 .
2020-02-01 19:07:02 -05:00
5cc11839b5
Add PROCASSWIRE error on behavioral assignments to wires, msg2737.
2018-11-26 17:58:18 -05:00
bb2822f4b5
Add --report-unoptflat, bug611.
...
Signed-off-by: Wilson Snyder <wsnyder@wsnyder.org>
2013-02-26 22:26:47 -05:00
Veripool API Bot
Wilson Snyder
Geza Lore
Yutetsu TAKATSUKASA
Jeremy Bennett