Veripool API Bot
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1f67080a1f
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Tests: Verilog format
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2026-03-09 21:39:16 -04:00 |
Wilson Snyder
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7c6c6a684b
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Add SPDX copyright identifiers, and get 'reuse' clean. No functional change.
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2026-01-26 20:24:34 -05:00 |
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Wilson Snyder
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48a12fb0f4
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Document and test `+verilator+rand+reset+2` usage (#6285 partial)
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2025-08-16 11:47:19 -04:00 |
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Wilson Snyder
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915ceb2d04
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Tests: Untabify tests. No functional change.
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2022-05-01 10:10:00 -04:00 |
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Wilson Snyder
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8952aa59ff
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Tests: Add force/release tests.
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2021-12-31 15:17:16 -05:00 |
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Wilson Snyder
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1ce360ed5b
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Add SPDX license identifiers. No functional change.
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2020-03-21 11:24:24 -04:00 |
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Wilson Snyder
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e26a75c59d
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Fix internal error on non-inlined inout pins.
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2011-02-07 19:15:58 -05:00 |