Veripool API Bot
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1f67080a1f
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Tests: Verilog format
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2026-03-09 21:39:16 -04:00 |
Wilson Snyder
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ba194f3790
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Tests: Avoid implied static variables, to avoid future warning
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2026-02-08 18:20:28 -05:00 |
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Wilson Snyder
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7c6c6a684b
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Add SPDX copyright identifiers, and get 'reuse' clean. No functional change.
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2026-01-26 20:24:34 -05:00 |
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Wilson Snyder
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e49ae663a6
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Fix constification of $realtobits, $bitstoreal (#4522).
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2023-09-28 22:45:00 -04:00 |
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Wilson Snyder
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1ce360ed5b
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Add SPDX license identifiers. No functional change.
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2020-03-21 11:24:24 -04:00 |
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Wilson Snyder
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c28a6eef3b
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Fix whitespace issues, bug1203.
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2017-09-11 19:18:58 -04:00 |
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Wilson Snyder
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385c166830
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Fix package logic var compile error.
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2013-01-17 19:04:36 -05:00 |
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Wilson Snyder
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410e6ff203
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Fix DECLFILENAME warning on .
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2013-01-17 18:38:51 -05:00 |
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Wilson Snyder
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3b39c3391d
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Support "import".
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2009-11-09 19:07:59 -05:00 |
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Wilson Snyder
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68567e763c
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Support "package" and $unit.
Add VARHIDDEN warning when signal name hides module name.
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2009-11-07 21:05:02 -05:00 |