Veripool API Bot
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1f67080a1f
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Tests: Verilog format
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2026-03-09 21:39:16 -04:00 |
Wilson Snyder
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7c6c6a684b
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Add SPDX copyright identifiers, and get 'reuse' clean. No functional change.
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2026-01-26 20:24:34 -05:00 |
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Wilson Snyder
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48a12fb0f4
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Document and test `+verilator+rand+reset+2` usage (#6285 partial)
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2025-08-16 11:47:19 -04:00 |
Yutetsu TAKATSUKASA
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b26658fd96
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Fix wrong optimization result of shifted out variable (#6016) (#6019)
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2025-05-18 07:18:37 -04:00 |
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Yutetsu TAKATSUKASA
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100e3d7702
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Fix const-bit-op-tree with single-bit masks (#5993) (#5998)
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2025-05-10 06:01:15 -04:00 |
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Wilson Snyder
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2c52119d6c
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Tests: Rename some tests into proper groups. No functional change.
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2024-09-21 10:04:58 -04:00 |