Veripool API Bot
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1f67080a1f
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Tests: Verilog format
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2026-03-09 21:39:16 -04:00 |
Wilson Snyder
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7c6c6a684b
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Add SPDX copyright identifiers, and get 'reuse' clean. No functional change.
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2026-01-26 20:24:34 -05:00 |
Iztok Jeras
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2aa6a229ca
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Change range order warning from LITENDIAN to ASCRANGE (#4010)
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2023-03-20 20:44:11 -04:00 |
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Wilson Snyder
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915ceb2d04
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Tests: Untabify tests. No functional change.
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2022-05-01 10:10:00 -04:00 |
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Wilson Snyder
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1ce360ed5b
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Add SPDX license identifiers. No functional change.
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2020-03-21 11:24:24 -04:00 |
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Wilson Snyder
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e5af46d3fb
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Add warning on slice selection out of bounds, bug875.
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2015-01-25 16:32:46 -05:00 |
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Wilson Snyder
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1856cad816
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Maintain little endian indication for multidimensional arrays
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2013-01-17 23:21:07 -05:00 |
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Wilson Snyder
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7ea8b54210
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Tests: Support atsim and cleanup verilator-only tests
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2010-03-18 12:03:08 -04:00 |
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Wilson Snyder
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266b3b8678
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Tests: Move old-style test_v's t_arith, etc to test_regress area
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2010-01-09 21:19:30 -05:00 |