Maintain little endian indication for multidimensional arrays

src/V3Width.cpp

@@ -370,16 +370,9 @@ private:
 	int msb = nodep->msbConst();
 	int lsb = nodep->lsbConst();
 	if (msb<lsb) {
-	    // If it's an array, ok to have either ordering, we'll just correct
-	    // So, see if we're sitting under a variable's arrayp.
-	    AstNode* huntbackp = nodep;
-	    while (huntbackp->backp()->castRange()) huntbackp=huntbackp->backp();
-	    if (huntbackp->backp()->castNodeArrayDType()) {
-	    } else {
-		// Little endian bits are legal, just remember to swap
-		// Warning is in V3Width to avoid false warnings when in "off" generate if's
-		nodep->littleEndian(!nodep->littleEndian());
-	    }
+	    // Little endian bits are legal, just remember to swap
+	    // Warning is in V3Width to avoid false warnings when in "off" generate if's
+	    nodep->littleEndian(!nodep->littleEndian());
 	    // Internally we'll always have msb() be the greater number
 	    // We only need to correct when doing [] AstSel extraction,
 	    // and when tracing the vector.

test_regress/t/t_func_lib_sub.v

@@ -17,7 +17,7 @@ reg covfok;
 reg [15:0] xwieqw;
 reg [2:0] ofnjjt;
 
-reg [37:0] hdsejo[0:1];
+reg [37:0] hdsejo[1:0];
 
 reg wxxzgd, tceppr, ratebp, fjizkr, iwwrnq;
 reg vrqrih, ryyjxy;

test_regress/t/t_lint_blksync_loop.v

@@ -65,7 +65,7 @@ module reg_1r1w
 
     output [WIDTH-1:0] data_out;
 
-    reg [WIDTH-1:0] array [0:DEPTH-1];
+    reg [WIDTH-1:0] array [DEPTH-1:0];
     reg [ADRWID-1:0] ra_r, wa_r;
     reg [WIDTH-1:0]  data_in_r;
     reg             wr_r;

test_regress/t/t_mem_fifo.v

@@ -88,7 +88,9 @@ module fifo (/*AUTOARG*/
    reg [65:0] outData;
 
    // verilator lint_off VARHIDDEN
+   // verilator lint_off LITENDIAN
    reg [65:0] 	 fifo[0:fifoDepth-1];
+   // verilator lint_on LITENDIAN
    // verilator lint_on VARHIDDEN
 
    //reg [65:0] 	      temp;

test_regress/t/t_mem_first.v

@@ -11,11 +11,13 @@ module t (/*AUTOARG*/
    input clk;
    integer _mode;	initial _mode = 0;
 
+   // verilator lint_off LITENDIAN
    reg [7:0]  mem_narrow [0:31];  //surefire lint_off_line RD_WRT WRTWRT NBAJAM
    reg [77:0] mem_wide   [1024:0];  //surefire lint_off_line RD_WRT WRTWRT NBAJAM
    reg [7:0]  mem_dly_narrow [0:1];  //surefire lint_off_line RD_WRT WRTWRT NBAJAM
    reg [77:0] mem_dly_wide   [1:0];  //surefire lint_off_line RD_WRT WRTWRT NBAJAM
    reg [34:0] vec_wide;
+   // verilator lint_on LITENDIAN
 
    reg [31:0] wrd0 [15:0];
    wire [3:0] sel = 4'h3;

test_regress/t/t_mem_multidim.v

@@ -10,6 +10,7 @@ module t (/*AUTOARG*/
 
    input clk;
 
+   // verilator lint_off LITENDIAN
    // verilator lint_off BLKANDNBLK
    //               3    3    4
    reg [71:0] memw [2:0][1:3][5:2];
@@ -27,6 +28,7 @@ module t (/*AUTOARG*/
 
    integer    imem[2:0][1:3];
    reg [2:0]  cstyle[2];
+   // verilator lint_on  LITENDIAN
 
    initial begin
       for (i0=0; i0<3; i0=i0+1) begin

test_regress/t/t_mem_multiwire.v

@@ -10,7 +10,9 @@ module t (/*AUTOARG*/
 
    input clk;
 
+   // verilator lint_off LITENDIAN
    wire [7:0] array [2:0][1:3];
+   // verilator lint_on LITENDIAN
 
    integer cyc; initial cyc=0;
    integer    i0,i1,i2;

test_regress/t/t_mem_slot.v

@@ -14,7 +14,7 @@ module t_mem_slot (Clk, SlotIdx, BitToChange, BitVal, SlotToReturn, OutputVal);
    input  [1:0] SlotToReturn;
    output [1:0] OutputVal;
 
-   reg    [1:0] Array[0:2];
+   reg    [1:0] Array[2:0];
 
    always @(posedge Clk)
    begin

test_regress/t/t_param_repl.v

@@ -20,7 +20,9 @@ module t (/*AUTOARG*/
    parameter 		DWORDS_LOG2 = 7;
    parameter 		DWORDS = (1<<DWORDS_LOG2);
    parameter 		DBYTES=DBITS/8;
+   // verilator lint_off LITENDIAN
    reg [DBITS-1:0] mem [0:DWORDS-1];
+   // verilator lint_on LITENDIAN
 
    integer 	     i;
 

test_regress/t/t_sys_readmem.v

@@ -5,9 +5,11 @@
 
 module t;
 
+   // verilator lint_off LITENDIAN
    reg [5:0] binary_nostart [2:15];
    reg [5:0] binary_start [0:15];
    reg [175:0] hex [0:15];
+   // verilator lint_on LITENDIAN
 
    integer   i;
 

test_regress/t/t_sys_readmem_bad_addr.v

@@ -4,7 +4,7 @@
 // without warranty, 2003 by Wilson Snyder.
 
 module t;
-   reg [175:0] hex [0:15];
+   reg [175:0] hex [15:0];
 
    initial begin
       $readmemh("t/t_sys_readmem_bad_addr.mem", hex);

test_regress/t/t_sys_readmem_bad_digit.v

@@ -5,7 +5,7 @@
 
 module t;
 
-   reg [175:0] hex [0:15];
+   reg [175:0] hex [15:0];
 
    initial begin
       $readmemb("t/t_sys_readmem_bad_digit.mem", hex);

test_regress/t/t_sys_readmem_bad_end.v

@@ -5,7 +5,7 @@
 
 module t;
 
-   reg [175:0] hex [0:15];
+   reg [175:0] hex [15:0];
 
    integer   i;
 

test_regress/t/t_sys_readmem_bad_notfound.v

@@ -5,7 +5,7 @@
 
 module t;
 
-   reg [175:0] hex [0:15];
+   reg [175:0] hex [15:0];
 
    initial begin
       $readmemh("t/t_sys_readmem_bad_NOTFOUND.mem", hex);