4 Commits

Author	SHA1	Message	Date
Veripool API Bot	07ed6aef53	Tests: Verilog format	2026-03-08 18:26:40 -04:00
Wilson Snyder	7c6c6a684b	Add SPDX copyright identifiers, and get 'reuse' clean. No functional change.	2026-01-26 20:24:34 -05:00
Wilson Snyder	48a12fb0f4	Document and test `+verilator+rand+reset+2` usage (#6285 partial)	2025-08-16 11:47:19 -04:00
Arkadiusz Kozdra	72993ec3dd	Support cross-module clockvars access (#5184)	2024-06-30 15:19:02 -04:00