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5 Commits

Author SHA1 Message Date
Veripool API Bot 07ed6aef53 Tests: Verilog format 2026-03-08 18:26:40 -04:00
Wilson Snyder 9083b238e5 Tests: Fix execute file permissions. No test change. 2026-02-02 08:28:46 -05:00
Wilson Snyder 7c6c6a684b Add SPDX copyright identifiers, and get 'reuse' clean. No functional change. 2026-01-26 20:24:34 -05:00
Wilson Snyder 6e8bd3da19 Internals/Tests: Cleanup some missing dev coverage items 2025-10-11 12:54:55 -04:00
Geza Lore d330100542 Create implicit nets for inputs of gate primitives. 
Prior to this we failed to create implicit nets for inputs of gate
primitives, which is required by the standard (IEEE 1800-2017 6.10).
Note: outputs were covered due to being modeled as the LHS of
assignments, which do create implicit nets.
 2023-10-21 22:45:26 +01:00