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8706 Commits

Author SHA1 Message Date
Bartłomiej Chmiel 82fbb446ed
Improve coverage 
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
 2025-11-06 12:38:47 +01:00
Bartłomiej Chmiel 4815ef662c
Fixup 
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
 2025-11-06 11:54:52 +01:00
Bartłomiej Chmiel 4b31bdb08c
Simplify processVtx 
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
 2025-11-06 11:51:46 +01:00
Bartłomiej Chmiel 129a88fc70
V3AssertProp Commentary 
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
 2025-11-06 11:36:56 +01:00
Bartłomiej Chmiel 459333d835
Fix emitv 
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
 2025-11-06 10:55:17 +01:00
Bartłomiej Chmiel 129ccb44ae
Pass graph by reference 
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
 2025-11-06 10:54:05 +01:00
Bartłomiej Chmiel b0d5c85c06
Dump graph test 
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
 2025-11-06 10:48:19 +01:00
Bartłomiej Chmiel 3104f89665
Handle unexpected not in sequence 
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
 2025-11-06 10:41:30 +01:00
Bartłomiej Chmiel 4719eb9739
Renames, remove lambda 
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
 2025-11-06 10:19:49 +01:00
Bartłomiej Chmiel 1528a02395
Missing VL_DO_DANGLING 
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
 2025-11-06 10:13:58 +01:00
Bartłomiej Chmiel 4ea29d7069
Handling unexpected vertex 
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
 2025-11-06 10:12:23 +01:00
Bartłomiej Chmiel d9654fa2c6
Simplify pexpr clause delete 
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
 2025-11-06 10:08:36 +01:00
Bartłomiej Chmiel 6789cbb3bd
VL_RESTORER for m_inSampled 
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
 2025-11-06 10:07:00 +01:00
Bartłomiej Chmiel 29749b0c42
Remove __Vassert check 
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
 2025-11-06 10:05:31 +01:00
Bartłomiej Chmiel fad3bdcd7e
Move unsup checks to V3Width, handle standalone properties 
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
 2025-11-06 10:03:26 +01:00
Bartłomiej Chmiel b2b65472ad
Renames and review fixes 
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
 2025-11-05 14:43:02 +01:00
Bartłomiej Chmiel 37f0bd87d3
Apply autofix suggestions from code review 
Co-authored-by: Wilson Snyder <wsnyder@wsnyder.org>
 2025-11-05 08:25:10 -05:00
Bartłomiej Chmiel 61a1dd9531
Implement multi-expression inline sequences 
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
 2025-11-04 16:53:00 +01:00
Wilson Snyder ea75163567 Fix determining Verilator revision when within git submodules without tags. 2025-11-03 19:59:59 -05:00
Wilson Snyder 1d9c5c2c6b Fix determining Verilator revision when within git submodules without tags. 2025-11-03 18:36:20 -05:00
Wilson Snyder c299b71677 Commentary: Changes update 2025-11-03 18:27:18 -05:00
Krzysztof Bieganski 0eaa9ed144
Fix `--timing` with `--x-initial-edge` (#6603) (#6631) 
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
 2025-11-03 09:39:23 -05:00
Geza Lore faaa2db844
Fix merging of impure assignments in gate optimization (#6629) (#6630) 2025-11-03 07:29:39 -05:00
Geza Lore d3ca79368c
Internals: Replace AstMTaskBody with AstCFunc(#6280) (#6628) 
AstMTaskBody is somewhat redundant and is problematic for #6280. We used
to wrap all MTasks in a CFunc before emit anyway. Now we create that
CFunc when we create the ExecMTask in V3OrderParallel, and subsequently
use the CFunc to represent the contents of the MTask. Final output and
optimizations are the same, but internals are simplified to move
towards #6280.

No functional change.
 2025-11-03 06:32:03 +00:00
Geza Lore d066504bb9
Optimize away calls to empty functions (#6626) 2025-11-02 16:11:02 -05:00
Wilson Snyder 611ffbe04e devel release 2025-11-02 11:18:20 -05:00
Wilson Snyder 184f8f7920 Version bump 2025-11-02 11:12:46 -05:00
Wilson Snyder 89f0e1def0 Commentary 2025-11-02 10:48:48 -05:00
Wilson Snyder d49697a85f Tests: Redo uvm test and package to be version based and use uvm_info 2025-11-02 10:46:16 -05:00
Wilson Snyder c801237ce8 Add `--preproc-defines`. 2025-11-01 23:27:43 -04:00
Wilson Snyder 1d69c18e33 Internals: Fix verilated.mk duplicate rule 2025-11-01 23:22:08 -04:00
Wilson Snyder e089817951 Tests: Reanme dump test 2025-11-01 22:05:52 -04:00
Wilson Snyder d4aa00dbeb Change `--preproc-comments` to be new name of `--pp-comments` option. 2025-11-01 21:59:16 -04:00
Wilson Snyder e6cdaf112c Internals: Add `--dump-inputs` to make __inputs without needing `--debug` 2025-11-01 20:34:06 -04:00
Wilson Snyder 8750cdac73 Update UVM 1800.2 2017-1.1 waivers 2025-11-01 16:34:31 -04:00
Wilson Snyder 2b8c9a1cff Internals: Remove mis-merged duplicate Makefile targets 2025-11-01 14:19:29 -04:00
Wilson Snyder cd8af21915 Add lint-py type checking using mypy 2025-11-01 14:15:39 -04:00
Wilson Snyder 782fe1daf2 Internals: Add more python strict typing. No functional change intended 2025-11-01 14:14:56 -04:00
Wilson Snyder 5847b105a5 Internals: Run format-make 2025-11-01 14:12:47 -04:00
Wilson Snyder 330b2589ed Internals: Run format-yaml 2025-11-01 14:11:47 -04:00
Wilson Snyder 76ec35a8f6 Internals: Move max_procs to VtOs package. No test change intended. 2025-11-01 12:17:22 -04:00
Wilson Snyder 00ac706f67 Commentary: Changes update 2025-11-01 11:46:00 -04:00
Geza Lore 2e502aead8
Internals: Make all scheduling region use a single trigger vector. (#6620) 
The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now
it uses a single "extended" trigger vector where the top bits are what
used to be the used bits in the 'pre' trigger vector. Please see the
description above `TriggerKit`. Also move the extra triggers from the
low end to the high end in the trigger vectors.
 2025-11-01 15:43:20 +00:00
Paul Swirhun e27613ed45
Fix interface parameter access in parameter map (#6587) (#6621) (#6623) 
Co-authored-by: Paul Swirhun <paulswirhun@gmail.com>
 2025-10-31 23:06:26 -04:00
Paul Swirhun 847de990de
Tests: Fix sched_getaffinity fallback for MacOS (#6622) (#6624) 
Co-authored-by: Paul Swirhun <paulswirhun@gmail.com>
 2025-10-31 21:55:45 -04:00
Paul Swirhun 10935ee031
Fix HIERPARAM to be suppressed for interface ports (#6587) (#6609) 
Co-authored-by: Paul Swirhun <paulswirhun@gmail.com>
 2025-10-31 15:49:30 -04:00
Geza Lore 922223a9c3
Internals: Replace VlTriggerVec with unpacked array (#6616) 
Removed the VlTriggerVec type, and refactored to use an unpacked array
of 64-bit words instead. This means the trigger vector and its
operations are now the same as for any other unpacked array. The few
special functions required for operating on a trigger vector are now
generated in V3SchedTrigger as regular AstCFunc if needed.

No functional change intended, performance should be the same.
 2025-10-31 18:29:11 +00:00
Wilson Snyder 08330f5fe2 Fix constant-arrayed instance parameters (#6614). 2025-10-30 19:18:47 -04:00
github action 884b48578d Apply 'make format' 2025-10-30 22:42:18 +00:00
Wilson Snyder 85119cb32e Fix waiving messages with empty contents (#6610). 2025-10-30 18:41:18 -04:00