Fix constant-arrayed instance parameters (#6614).

This commit is contained in:
Wilson Snyder 2025-10-30 19:18:37 -04:00
parent 884b48578d
commit 08330f5fe2
4 changed files with 70 additions and 3 deletions

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@ -128,6 +128,7 @@ Verilator 5.041 devel
* Fix ENUMVALUE warning when overriding parameter using `-G/-pvalue` options. [Geza Lore]
* Fix `-G` and `-pvalue` with `--hierarchical`. [Geza Lore]
* Fix waiving messages with empty contents (#6610). [Yoshitomo KANEDA]
* Fix constant-arrayed instance parameters (#6614). [Alex Solomatnikov]
Verilator 5.040 2025-08-30

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@ -2954,9 +2954,12 @@ class WidthVisitor final : public VNVisitor {
// InitArray has type of the array; children are array values
if (m_vup->prelim()) { // First stage evaluation
AstNodeDType* const vdtypep = m_vup->dtypeNullp();
UASSERT_OBJ(vdtypep, nodep, "InitArray type not assigned by AstPattern/Var visitor");
nodep->dtypep(vdtypep);
const AstNodeDType* const arrayp = vdtypep->skipRefp();
if (!nodep->dtypep() || vdtypep) {
UASSERT_OBJ(vdtypep, nodep,
"InitArray type not assigned by AstPattern/Var visitor");
nodep->dtypep(vdtypep);
}
const AstNodeDType* const arrayp = nodep->dtypep()->skipRefp();
if (VN_IS(arrayp, NodeArrayDType) || VN_IS(arrayp, AssocArrayDType)) {
userIterateChildren(nodep, WidthVP{arrayp->subDTypep(), BOTH}.p());
} else {

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@ -0,0 +1,16 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile()
test.passes()

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@ -0,0 +1,47 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module p_i_match #(
parameter type S_IS_T,
parameter S_IS_T S_IS
) ();
endmodule
module ring #(
parameter type I_T
) ();
localparam int unsigned N_SS = (18 / 2) / 2;
localparam int unsigned N_P_IS = (18 / 2) - 1;
typedef int s_is_t[N_P_IS-1:0];
function automatic s_is_t gen_s_is();
for (int st = 0; st < N_SS; st++) begin
for (int i = 0; i < 2; i++) begin
if (st * 2 + i < N_P_IS) begin
int delta = ((st + 1) * 2) + i;
gen_s_is[st*2+i] = i;
end
end
end
endfunction
localparam s_is_t S_IS = gen_s_is();
p_i_match #(
.S_IS_T(s_is_t),
.S_IS(S_IS)
) p (
.*);
endmodule
module t;
typedef logic [4:0] i_t;
ring #(
.I_T(i_t)
) dut (
.*);
endmodule