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mirror of https://github.com/verilator/verilator.git synced 2026-10-06 10:03:44 +02:00
Code Issues Packages Projects Releases Wiki Activity
10,513 Commits 3 Branches 171 Tags
303ebe861bb70bc6bc5076edda6b84ef0a4b4cf5
Commit Graph
10 Commits
Author SHA1 Message Date
Veripool API Bot ce4d35aa85 Verilog format 2026-03-03 07:21:24 -05:00
Wilson Snyder 7c6c6a684b Add SPDX copyright identifiers, and get 'reuse' clean. No functional change. 2026-01-26 20:24:34 -05:00
Wilson Snyder 907047d823 Tests: Remove unneeded AUTOARGS. No test change. 2025-09-13 09:28:43 -04:00
Wilson Snyder 85454f6083 Fix wire array with initial assignment (#6391). 2025-09-05 17:31:17 -04:00
Iztok Jeras 2aa6a229ca Change range order warning from LITENDIAN to ASCRANGE (#4010) 2023-03-20 20:44:11 -04:00
Wilson Snyder 1ce360ed5b Add SPDX license identifiers. No functional change. 2020-03-21 11:24:24 -04:00
Wilson Snyder cac50282eb Fix pattern replication without key. 2020-01-26 11:38:34 -05:00
Wilson Snyder 446b0e4e5e Support '{} assignment pattern on arrays, bug355. 2014-03-30 20:41:20 -04:00
Wilson Snyder 17b8b660f0 Internals: Fix assignment pattern replication. From bug355 branch. 2014-03-30 10:20:12 -04:00
Wilson Snyder 8a708f52f7 Tests: Merge from pattern branch. 2013-12-21 08:29:04 -05:00
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