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Fix wire array with initial assignment (#6391).

This commit is contained in:
Wilson Snyder 2025-09-05 17:31:17 -04:00
parent 141de7b94a
commit 85454f6083
3 changed files with 12 additions and 0 deletions
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@ -19,6 +19,7 @@ Verilator 5.041 devel
* Fix randomize local after parameters applied (#6371). [Alex Solomatnikov]
* Fix package imports not found after parameters applied (#6373). [Alex Solomatnikov]
* Fix COVERAGEIGN-ignored `get_inst_coverage` and other covergroup methods (#6383). [Alex Solomatnikov]
* Fix wire array with initial assignment (#6391). [Alex Solomatnikov]
Verilator 5.040 2025-08-30

7
src/verilog.y
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@ -3267,6 +3267,13 @@ netSig<varp>: // IEEE: net_decl_assignment - one element from
AstNode::addNext<AstNode, AstNode>($$, assignp); }
| netId variable_dimensionList sigAttrListE
{ $$ = VARDONEA($<fl>1, *$1, $2, $3); }
| netId variable_dimensionList sigAttrListE '=' expr
{ AstDelay* const delayp = GRAMMARP->getNetDelay();
AstAssignW* const assignp = new AstAssignW{$4, new AstParseRef{$<fl>1, VParseRefExp::PX_TEXT, *$1}, $5, delayp};
$$ = VARDONEA($<fl>1, *$1, $2, $3);
if (delayp) GRAMMARP->setNetDelay(delayp->cloneTree(false));
if (GRAMMARP->m_netStrengthp) assignp->strengthSpecp(GRAMMARP->m_netStrengthp->cloneTree(false));
AstNode::addNext<AstNode, AstNode>($$, assignp); }
;
netId<strp>:

4
test_regress/t/t_array_pattern_unpacked.v
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@ -7,10 +7,14 @@
module t (/*AUTOARG*/);
logic [3:0] array_simp [1:0] [3:0]; // descending range array
wire [2:0] array_wire [1:0] = '{3'd1, 3'd2};
int irep[1:2][1:6];
initial begin
if (array_wire[0] !== 3'd2) $stop;
if (array_wire[1] !== 3'd1) $stop;
array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0};
if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]}
!== 16'h3210) $stop;