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9,643 Commits 2 Branches 170 Tags
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7 Commits
Author SHA1 Message Date
Veripool API Bot 1f67080a1f Tests: Verilog format 2026-03-09 21:39:16 -04:00
Wilson Snyder 7c6c6a684b Add SPDX copyright identifiers, and get 'reuse' clean. No functional change. 2026-01-26 20:24:34 -05:00
Wilson Snyder 48a12fb0f4 Document and test +verilator+rand+reset+2 usage (#6285 partial) 2025-08-16 11:47:19 -04:00
Iztok Jeras 2aa6a229ca Change range order warning from LITENDIAN to ASCRANGE (#4010) 2023-03-20 20:44:11 -04:00
Wilson Snyder 915ceb2d04 Tests: Untabify tests. No functional change. 2022-05-01 10:10:00 -04:00
Wilson Snyder 1ce360ed5b Add SPDX license identifiers. No functional change. 2020-03-21 11:24:24 -04:00
Todd Strader 5e54d3e41a Fix interface inside generate, bug1001, bug1003. 
Signed-off-by: Wilson Snyder <[email protected]>
 2015-12-05 19:39:40 -05:00