From ffa87540cc314f59600b74c74eaecea43791ee87 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 20 Dec 2025 21:25:01 -0500
Subject: [PATCH] Fix randcase under fork (#6843).

---
 Changes                           |  1 +
 src/V3Randomize.cpp               |  1 +
 test_regress/t/t_randcase_fork.py | 18 ++++++++++++++++++
 test_regress/t/t_randcase_fork.v  | 24 ++++++++++++++++++++++++
 4 files changed, 44 insertions(+)
 create mode 100755 test_regress/t/t_randcase_fork.py
 create mode 100644 test_regress/t/t_randcase_fork.v

diff --git a/Changes b/Changes
index 4ae4b59fa..d2c225244 100644
--- a/Changes
+++ b/Changes
@@ -111,6 +111,7 @@ Verilator 5.043 devel
 * Fix nested struct within parameter port list (#6818) (#6824). [Luca Colagrande]
 * Fix duplicate name error with interface initial blocks (#6804) (#6805). [Thomas Dybdahl Ahle]
 * Fix firing array selects of events (#6829). [Amal Araweelo Almis]
+* Fix randcase under fork (#6843). [Amal Araweelo Almis]
 
 
 Verilator 5.042 2025-11-02
diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp
index 624176bc9..556f5abd0 100644
--- a/src/V3Randomize.cpp
+++ b/src/V3Randomize.cpp
@@ -2634,6 +2634,7 @@ class RandomizeVisitor final : public VNVisitor {
         const std::string name = "__Vrandcase" + cvtToStr(m_randCaseNum++);
         AstVar* const randVarp = new AstVar{fl, VVarType::BLOCKTEMP, name, sumDTypep};
         randVarp->noSubst(true);
+        randVarp->lifetime(VLifetime::AUTOMATIC_EXPLICIT);
         if (m_ftaskp) randVarp->funcLocal(true);
         AstNodeExpr* sump = new AstConst{fl, AstConst::WidthedValue{}, 64, 0};
         AstNodeIf* const firstIfsp
diff --git a/test_regress/t/t_randcase_fork.py b/test_regress/t/t_randcase_fork.py
new file mode 100755
index 000000000..ac142fe63
--- /dev/null
+++ b/test_regress/t/t_randcase_fork.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator_st')
+
+test.compile(verilator_flags2=['--binary'])
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_randcase_fork.v b/test_regress/t/t_randcase_fork.v
new file mode 100644
index 000000000..499a56273
--- /dev/null
+++ b/test_regress/t/t_randcase_fork.v
@@ -0,0 +1,24 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module randcase_tb;
+  int count;
+  initial begin
+    for (int i = 0; i < 100; i++) begin
+      fork
+        randcase
+          1: count++;
+          5: count--;
+          3: ;
+        endcase
+      join_none
+    end
+    #1;
+    if (count > 30) $stop;  // Realistically won't happen (10^25) though not impossible
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule