Add FSM arc coverage to verilator_coverage .info output
Signed-off-by: Igor Zaworski <izaworski@antmicro.com>
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@ -262,7 +262,6 @@ void VlcTop::writeInfo(const string& filename) {
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uint64_t daCount = 0;
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std::vector<const VlcPoint*> infoPoints;
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for (const auto& point : sc.points()) {
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if (point->isFsmArc()) continue;
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daCount = std::max(daCount, point->count());
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infoPoints.push_back(point);
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}
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@ -272,10 +271,14 @@ void VlcTop::writeInfo(const string& filename) {
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int point_num = 0;
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for (const VlcPoint* point : infoPoints) {
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os << "BRDA:" << sc.lineno() << ",";
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os << "0,";
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if (point->comment().empty()) {
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if (point->isFsmArc()) {
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os << "2,";
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os << point->fsmFromState() << "->" << point->fsmToState();
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} else if (point->comment().empty()) {
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os << "0,";
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os << point_num;
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} else {
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os << (point->isFsmState() ? '1' : '0') << ',';
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std::string comment(point->comment());
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std::replace(comment.begin(), comment.end(), ',', '_');
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os << comment;
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@ -0,0 +1,11 @@
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TN:verilator_coverage
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SF:t/t_cover_fsm_basic.v
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DA:45,4
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BRDA:45,2,ANY->S_IDLE,1
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BRDA:45,2,S_DONE->S_DONE,4
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BRDA:45,2,S_IDLE->S_IDLE,3
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BRDA:45,2,S_IDLE->S_RUN,1
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BRDA:45,2,S_RUN->S_DONE,1
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BRF:5
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BRH:0
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end_of_record
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@ -0,0 +1,22 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('dist')
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test.run(cmd=[
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os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--write-info",
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test.obj_dir + "/coverage.info", "--filter-type fsm_arc", "t/t_vlcov_data_g.dat"
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],
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verilator_run=True)
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test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out")
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test.passes()
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