From f511f6c34d043fa5387e6775cb5b2ca8bccfb189 Mon Sep 17 00:00:00 2001
From: Igor Zaworski <izaworski@antmicro.com>
Date: Wed, 22 Jul 2026 18:26:14 +0200
Subject: [PATCH] Add FSM arc coverage to verilator_coverage .info output

Signed-off-by: Igor Zaworski <izaworski@antmicro.com>
---
 src/VlcTop.cpp                              |  9 ++++++---
 test_regress/t/t_vlcov_opt_fsm_arc.info.out | 11 +++++++++++
 test_regress/t/t_vlcov_opt_fsm_arc.py       | 22 +++++++++++++++++++++
 3 files changed, 39 insertions(+), 3 deletions(-)
 create mode 100644 test_regress/t/t_vlcov_opt_fsm_arc.info.out
 create mode 100755 test_regress/t/t_vlcov_opt_fsm_arc.py

diff --git a/src/VlcTop.cpp b/src/VlcTop.cpp
index 70a0a7f7d..e6f2edad4 100644
--- a/src/VlcTop.cpp
+++ b/src/VlcTop.cpp
@@ -262,7 +262,6 @@ void VlcTop::writeInfo(const string& filename) {
             uint64_t daCount = 0;
             std::vector<const VlcPoint*> infoPoints;
             for (const auto& point : sc.points()) {
-                if (point->isFsmArc()) continue;
                 daCount = std::max(daCount, point->count());
                 infoPoints.push_back(point);
             }
@@ -272,10 +271,14 @@ void VlcTop::writeInfo(const string& filename) {
             int point_num = 0;
             for (const VlcPoint* point : infoPoints) {
                 os << "BRDA:" << sc.lineno() << ",";
-                os << "0,";
-                if (point->comment().empty()) {
+                if (point->isFsmArc()) {
+                    os << "2,";
+                    os << point->fsmFromState() << "->" << point->fsmToState();
+                } else if (point->comment().empty()) {
+                    os << "0,";
                     os << point_num;
                 } else {
+                    os << (point->isFsmState() ? '1' : '0') << ',';
                     std::string comment(point->comment());
                     std::replace(comment.begin(), comment.end(), ',', '_');
                     os << comment;
diff --git a/test_regress/t/t_vlcov_opt_fsm_arc.info.out b/test_regress/t/t_vlcov_opt_fsm_arc.info.out
new file mode 100644
index 000000000..db73957d1
--- /dev/null
+++ b/test_regress/t/t_vlcov_opt_fsm_arc.info.out
@@ -0,0 +1,11 @@
+TN:verilator_coverage
+SF:t/t_cover_fsm_basic.v
+DA:45,4
+BRDA:45,2,ANY->S_IDLE,1
+BRDA:45,2,S_DONE->S_DONE,4
+BRDA:45,2,S_IDLE->S_IDLE,3
+BRDA:45,2,S_IDLE->S_RUN,1
+BRDA:45,2,S_RUN->S_DONE,1
+BRF:5
+BRH:0
+end_of_record
diff --git a/test_regress/t/t_vlcov_opt_fsm_arc.py b/test_regress/t/t_vlcov_opt_fsm_arc.py
new file mode 100755
index 000000000..147480bbb
--- /dev/null
+++ b/test_regress/t/t_vlcov_opt_fsm_arc.py
@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('dist')
+
+test.run(cmd=[
+    os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--write-info",
+    test.obj_dir + "/coverage.info", "--filter-type fsm_arc", "t/t_vlcov_data_g.dat"
+],
+         verilator_run=True)
+
+test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out")
+
+test.passes()