From f41e36b99fcb486e59b8b421f8a594dfc0205482 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 6 Sep 2025 07:51:49 -0400 Subject: [PATCH] Commentary: Convert docs examples to 2 space indents. --- docs/gen/ex_BADVLTPRAGMA_faulty.rst | 2 +- docs/gen/ex_BADVLTPRAGMA_msg.rst | 6 +- docs/gen/ex_DIDNOTCONVERGE_faulty.rst | 4 +- docs/gen/ex_MULTIDRIVEN_faulty.rst | 12 +- docs/gen/ex_MULTIDRIVEN_msg.rst | 6 +- docs/gen/ex_PROCASSINIT_faulty.rst | 12 +- docs/gen/ex_PROCASSINIT_fixed.rst | 18 +-- docs/gen/ex_PROCASSINIT_msg.rst | 14 +-- docs/gen/ex_STMTDLY_faulty.rst | 2 +- docs/gen/ex_STMTDLY_msg.rst | 2 +- docs/gen/ex_USERERROR_faulty.rst | 2 +- docs/gen/ex_USERERROR_msg.rst | 2 +- docs/gen/ex_USERFATAL_faulty.rst | 2 +- docs/gen/ex_USERFATAL_msg.rst | 2 +- docs/gen/ex_USERINFO_faulty.rst | 2 +- docs/gen/ex_USERINFO_msg.rst | 2 +- docs/gen/ex_USERWARN_faulty.rst | 2 +- docs/gen/ex_USERWARN_msg.rst | 2 +- docs/gen/ex_VARHIDDEN_faulty.rst | 2 +- docs/gen/ex_VARHIDDEN_msg.rst | 2 +- docs/guide/connecting.rst | 12 +- docs/guide/extensions.rst | 10 +- docs/guide/install.rst | 42 +++---- docs/guide/warnings.rst | 130 ++++++++++----------- test_regress/t/t_assert_comp_bad.out | 60 +++++----- test_regress/t/t_assert_comp_bad.v | 30 ++--- test_regress/t/t_lint_badvltpragma_bad.out | 6 +- test_regress/t/t_lint_badvltpragma_bad.v | 4 +- test_regress/t/t_lint_didnotconverge_bad.v | 16 +-- test_regress/t/t_lint_multidriven_bad.out | 28 ++--- test_regress/t/t_lint_multidriven_bad.v | 52 ++++----- test_regress/t/t_lint_procassinit_bad.out | 26 ++--- test_regress/t/t_lint_procassinit_bad.v | 74 ++++++------ test_regress/t/t_lint_stmtdly_bad.out | 6 +- test_regress/t/t_lint_stmtdly_bad.v | 8 +- test_regress/t/t_var_bad_hide_docs.out | 6 +- test_regress/t/t_var_bad_hide_docs.v | 2 +- 37 files changed, 305 insertions(+), 305 deletions(-) diff --git a/docs/gen/ex_BADVLTPRAGMA_faulty.rst b/docs/gen/ex_BADVLTPRAGMA_faulty.rst index 62725c09b..ae8a322c2 100644 --- a/docs/gen/ex_BADVLTPRAGMA_faulty.rst +++ b/docs/gen/ex_BADVLTPRAGMA_faulty.rst @@ -2,4 +2,4 @@ .. code-block:: sv :emphasize-lines: 1 - // verilator lintt_off WIDTH //<--- Warning (lint_off misspelled) + // verilator lintt_off WIDTH //<--- Warning (lint_off misspelled) diff --git a/docs/gen/ex_BADVLTPRAGMA_msg.rst b/docs/gen/ex_BADVLTPRAGMA_msg.rst index ea57d297e..28e1139af 100644 --- a/docs/gen/ex_BADVLTPRAGMA_msg.rst +++ b/docs/gen/ex_BADVLTPRAGMA_msg.rst @@ -2,6 +2,6 @@ .. code-block:: :emphasize-lines: 1,2 - %Error-BADVLTPRAGMA: example.v:1:4 Unknown verilator comment: '/*verilator lintt_off WIDTH <--- Warning (lint_off misspelled)*/' - 7 | /*verilator lintt_off WIDTH <--- Warning (lint_off misspelled)*/ - | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + %Error-BADVLTPRAGMA: example.v:1:3 Unknown verilator comment: '/*verilator lintt_off WIDTH <--- Warning (lint_off misspelled)*/' + 7 | /*verilator lintt_off WIDTH <--- Warning (lint_off misspelled)*/ + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/gen/ex_DIDNOTCONVERGE_faulty.rst b/docs/gen/ex_DIDNOTCONVERGE_faulty.rst index e37f06208..3c1303cc9 100644 --- a/docs/gen/ex_DIDNOTCONVERGE_faulty.rst +++ b/docs/gen/ex_DIDNOTCONVERGE_faulty.rst @@ -2,5 +2,5 @@ .. code-block:: sv :linenos: - always_comb b = ~a; - always_comb a = b; + always_comb b = ~a; + always_comb a = b; diff --git a/docs/gen/ex_MULTIDRIVEN_faulty.rst b/docs/gen/ex_MULTIDRIVEN_faulty.rst index 0be24327d..4f28b638c 100644 --- a/docs/gen/ex_MULTIDRIVEN_faulty.rst +++ b/docs/gen/ex_MULTIDRIVEN_faulty.rst @@ -3,9 +3,9 @@ :linenos: :emphasize-lines: 2,5 - always @(posedge clk) begin - out2[7:0] <= d0; // <--- Warning - end - always @(negedge clk) begin - out2[15:8] <= d0; // <--- Warning - end + always @(posedge clk) begin + out2[7:0] <= d0; // <--- Warning + end + always @(negedge clk) begin + out2[15:8] <= d0; // <--- Warning + end diff --git a/docs/gen/ex_MULTIDRIVEN_msg.rst b/docs/gen/ex_MULTIDRIVEN_msg.rst index a2b090f34..0dbbca0da 100644 --- a/docs/gen/ex_MULTIDRIVEN_msg.rst +++ b/docs/gen/ex_MULTIDRIVEN_msg.rst @@ -1,6 +1,6 @@ .. comment: generated by t_lint_multidriven_bad .. code-block:: - %Warning-MULTIDRIVEN: example.v:1:22 Signal has multiple driving blocks with different clocking: 'out2' - example.v:1:7 ... Location of first driving block - example.v:1:7 ... Location of other driving block + %Warning-MULTIDRIVEN: example.v:1:21 Signal has multiple driving blocks with different clocking: 'out2' + example.v:1:5 ... Location of first driving block + example.v:1:5 ... Location of other driving block diff --git a/docs/gen/ex_PROCASSINIT_faulty.rst b/docs/gen/ex_PROCASSINIT_faulty.rst index c21130841..3148f215f 100644 --- a/docs/gen/ex_PROCASSINIT_faulty.rst +++ b/docs/gen/ex_PROCASSINIT_faulty.rst @@ -3,10 +3,10 @@ :linenos: :emphasize-lines: 1,5 - logic flop_out = 1; // <--- Warning + logic flop_out = 1; // <--- Warning - always @(posedge clk, negedge reset_l) begin - if (enable) begin - flop_out <= ~in; // <--- Use of initialized - end - end + always @(posedge clk, negedge reset_l) begin + if (enable) begin + flop_out <= ~in; // <--- Use of initialized + end + end diff --git a/docs/gen/ex_PROCASSINIT_fixed.rst b/docs/gen/ex_PROCASSINIT_fixed.rst index f5a3f3711..0a162e5a9 100644 --- a/docs/gen/ex_PROCASSINIT_fixed.rst +++ b/docs/gen/ex_PROCASSINIT_fixed.rst @@ -3,13 +3,13 @@ :linenos: :emphasize-lines: 5 - logic flop2_out; + logic flop2_out; - always @(posedge clk, negedge reset_l) begin - if (!reset_l) begin - flop2_out <= '1; // <--- Added reset init - end - else if (enable) begin - flop2_out <= ~in; - end - end + always @(posedge clk, negedge reset_l) begin + if (!reset_l) begin + flop2_out <= '1; // <--- Added reset init + end + else if (enable) begin + flop2_out <= ~in; + end + end diff --git a/docs/gen/ex_PROCASSINIT_msg.rst b/docs/gen/ex_PROCASSINIT_msg.rst index 4fe084952..769c5d295 100644 --- a/docs/gen/ex_PROCASSINIT_msg.rst +++ b/docs/gen/ex_PROCASSINIT_msg.rst @@ -1,12 +1,12 @@ .. comment: generated by t_lint_procassinit_bad .. code-block:: - %Warning-PROCASSINIT: example.v:1:21 Procedural assignment to declaration with initial value: 'flop_out' + %Warning-PROCASSINIT: example.v:1:20 Procedural assignment to declaration with initial value: 'flop_out' : ... note: In instance 't' : ... Location of variable initialization - 26 | logic flop_out = 1; - | ^ - example.v:1:10 ... Location of variable process write - : ... Perhaps should initialize instead using a reset in this process - 30 | flop_out <= ~in; - | ^~~~~~~~ + 26 | logic flop_out = 1; + | ^ + example.v:1:7 ... Location of variable process write + : ... Perhaps should initialize instead using a reset in this process + 30 | flop_out <= ~in; + | ^~~~~~~~ diff --git a/docs/gen/ex_STMTDLY_faulty.rst b/docs/gen/ex_STMTDLY_faulty.rst index 97fcc43e9..431e8b297 100644 --- a/docs/gen/ex_STMTDLY_faulty.rst +++ b/docs/gen/ex_STMTDLY_faulty.rst @@ -2,4 +2,4 @@ .. code-block:: sv :emphasize-lines: 1 - #100 $finish; //<--- Warning + #100 $finish; //<--- Warning diff --git a/docs/gen/ex_STMTDLY_msg.rst b/docs/gen/ex_STMTDLY_msg.rst index 15ceefa58..730500051 100644 --- a/docs/gen/ex_STMTDLY_msg.rst +++ b/docs/gen/ex_STMTDLY_msg.rst @@ -1,4 +1,4 @@ .. comment: generated by t_lint_stmtdly_bad .. code-block:: - %Warning-STMTDLY: example.v:1:7 Ignoring delay on this statement due to --no-timing + %Warning-STMTDLY: example.v:1:5 Ignoring delay on this statement due to --no-timing diff --git a/docs/gen/ex_USERERROR_faulty.rst b/docs/gen/ex_USERERROR_faulty.rst index fdd1a5978..a1e1aa4e4 100644 --- a/docs/gen/ex_USERERROR_faulty.rst +++ b/docs/gen/ex_USERERROR_faulty.rst @@ -1,4 +1,4 @@ .. comment: generated by t_assert_comp_bad .. code-block:: sv - $error("User elaboration-time error"); + $error("User elaboration-time error"); diff --git a/docs/gen/ex_USERERROR_msg.rst b/docs/gen/ex_USERERROR_msg.rst index 386c97e57..43f5da266 100644 --- a/docs/gen/ex_USERERROR_msg.rst +++ b/docs/gen/ex_USERERROR_msg.rst @@ -1,4 +1,4 @@ .. comment: generated by t_assert_comp_bad .. code-block:: - %Warning-USERERROR: example.v:1:7 User elaboration-time error + %Warning-USERERROR: example.v:1:5 User elaboration-time error diff --git a/docs/gen/ex_USERFATAL_faulty.rst b/docs/gen/ex_USERFATAL_faulty.rst index 2900b81b7..19cba571f 100644 --- a/docs/gen/ex_USERFATAL_faulty.rst +++ b/docs/gen/ex_USERFATAL_faulty.rst @@ -1,4 +1,4 @@ .. comment: generated by t_assert_comp_bad .. code-block:: sv - $fatal(0, "User elaboration-time fatal"); + $fatal(0, "User elaboration-time fatal"); diff --git a/docs/gen/ex_USERFATAL_msg.rst b/docs/gen/ex_USERFATAL_msg.rst index 29fc57c93..0417e30ee 100644 --- a/docs/gen/ex_USERFATAL_msg.rst +++ b/docs/gen/ex_USERFATAL_msg.rst @@ -1,4 +1,4 @@ .. comment: generated by t_assert_comp_bad .. code-block:: - %Warning-USERFATAL: example.v:1:7 User elaboration-time fatal + %Warning-USERFATAL: example.v:1:5 User elaboration-time fatal diff --git a/docs/gen/ex_USERINFO_faulty.rst b/docs/gen/ex_USERINFO_faulty.rst index ab9701e08..0d6ff4fb6 100644 --- a/docs/gen/ex_USERINFO_faulty.rst +++ b/docs/gen/ex_USERINFO_faulty.rst @@ -1,4 +1,4 @@ .. comment: generated by t_assert_comp_bad .. code-block:: sv - $info("User elaboration-time info"); + $info("User elaboration-time info"); diff --git a/docs/gen/ex_USERINFO_msg.rst b/docs/gen/ex_USERINFO_msg.rst index c30d89ec3..c5d299d20 100644 --- a/docs/gen/ex_USERINFO_msg.rst +++ b/docs/gen/ex_USERINFO_msg.rst @@ -1,4 +1,4 @@ .. comment: generated by t_assert_comp_bad .. code-block:: - -Info: example.v:1:7 User elaboration-time info + -Info: example.v:1:5 User elaboration-time info diff --git a/docs/gen/ex_USERWARN_faulty.rst b/docs/gen/ex_USERWARN_faulty.rst index fc2fb53fa..dc2316999 100644 --- a/docs/gen/ex_USERWARN_faulty.rst +++ b/docs/gen/ex_USERWARN_faulty.rst @@ -1,4 +1,4 @@ .. comment: generated by t_assert_comp_bad .. code-block:: sv - $warning("User elaboration-time warning"); + $warning("User elaboration-time warning"); diff --git a/docs/gen/ex_USERWARN_msg.rst b/docs/gen/ex_USERWARN_msg.rst index e54250fdd..eb1997dea 100644 --- a/docs/gen/ex_USERWARN_msg.rst +++ b/docs/gen/ex_USERWARN_msg.rst @@ -1,4 +1,4 @@ .. comment: generated by t_assert_comp_bad .. code-block:: - %Warning-USERWARN: example.v:1:7 User elaboration-time warning + %Warning-USERWARN: example.v:1:5 User elaboration-time warning diff --git a/docs/gen/ex_VARHIDDEN_faulty.rst b/docs/gen/ex_VARHIDDEN_faulty.rst index b982e6c90..036636d48 100644 --- a/docs/gen/ex_VARHIDDEN_faulty.rst +++ b/docs/gen/ex_VARHIDDEN_faulty.rst @@ -4,5 +4,5 @@ :emphasize-lines: 2 module t; - integer t; //<--- Warning ('t' hidden by module 't') + integer t; //<--- Warning ('t' hidden by module 't') endmodule diff --git a/docs/gen/ex_VARHIDDEN_msg.rst b/docs/gen/ex_VARHIDDEN_msg.rst index 08d7a5b9a..be48b7400 100644 --- a/docs/gen/ex_VARHIDDEN_msg.rst +++ b/docs/gen/ex_VARHIDDEN_msg.rst @@ -1,5 +1,5 @@ .. comment: generated by t_var_bad_hide_docs .. code-block:: - %Warning-VARHIDDEN: example.v:2:12 Declaration of signal hides declaration in upper scope: 't' + %Warning-VARHIDDEN: example.v:2:11 Declaration of signal hides declaration in upper scope: 't' example.v:1:8 ... Location of original declaration diff --git a/docs/guide/connecting.rst b/docs/guide/connecting.rst index 9a06bd3cf..fa1821d00 100644 --- a/docs/guide/connecting.rst +++ b/docs/guide/connecting.rst @@ -184,7 +184,7 @@ Verilog, put in our.v: import "DPI-C" function int add (input int a, input int b); initial begin - $display("%x + %x = %x", 1, 2, add(1,2)); + $display("%x + %x = %x", 1, 2, add(1,2)); endtask Then after Verilating, Verilator will create a file Vour__Dpi.h with the @@ -225,8 +225,8 @@ called from C++: export "DPI-C" task publicSetBool; task publicSetBool; - input bit in_bool; - var_bool = in_bool; + input bit in_bool; + var_bool = in_bool; endtask Then after Verilating, Verilator will create a file Vour__Dpi.h with the @@ -294,11 +294,11 @@ wrapper: import "DPI-C" context function void dpi_that_accesses_din(); always @(...) - dpi_din_args(din); + dpi_din_args(din); task dpi_din_args(input din); - /* verilator no_inline_task */ - dpi_that_accesses_din(); + // verilator no_inline_task + dpi_that_accesses_din(); endtask diff --git a/docs/guide/extensions.rst b/docs/guide/extensions.rst index dae79bdea..83a710f6c 100644 --- a/docs/guide/extensions.rst +++ b/docs/guide/extensions.rst @@ -240,7 +240,7 @@ or "`ifdef`"'s may break other tools. reg enable_r /*verilator clock_enable*/; wire gated_clk = clk & enable_r; always_ff @(posedge clk) - enable_r <= enable_early; + enable_r <= enable_early; The clock_enable attribute will cause the clock gate to be ignored in the scheduling algorithm, sometimes required for correct clock behavior, @@ -331,8 +331,8 @@ or "`ifdef`"'s may break other tools. // Note the placement of the semicolon above always_comb begin if (....) begin - splitme = ....; - other assignments + splitme = ....; + other assignments end end @@ -346,13 +346,13 @@ or "`ifdef`"'s may break other tools. // All assignments excluding those to splitme always_comb begin if (....) begin - other assignments + other assignments end end // All assignments to splitme always_comb begin if (....) begin - splitme = ....; + splitme = ....; end end diff --git a/docs/guide/install.rst b/docs/guide/install.rst index 57e9f72cd..0413ba4d7 100644 --- a/docs/guide/install.rst +++ b/docs/guide/install.rst @@ -19,7 +19,7 @@ started. (Note distribution packages almost never have the most recent Verilator version, so we recommend following :ref:`Git Install` below, instead.) To install as a package: -.. code-block:: shell +.. code-block:: bash apt-get install verilator # On Ubuntu @@ -56,7 +56,7 @@ options and details, see :ref:`Detailed Build Instructions` below. In brief, to install from git: -.. code-block:: shell +.. code-block:: bash # Prerequisites: #sudo apt-get install git help2man perl python3 make autoconf g++ flex bison ccache @@ -109,7 +109,7 @@ Install Prerequisites To build or run Verilator, you need these standard packages: -.. code-block:: shell +.. code-block:: bash sudo apt-get install git help2man perl python3 make sudo apt-get install g++ # Alternatively, clang @@ -120,27 +120,27 @@ To build or run Verilator, you need these standard packages: For SystemC: -.. code-block:: shell +.. code-block:: bash sudo apt-get install libsystemc libsystemc-dev For constraints: -.. code-block:: shell +.. code-block:: bash sudo apt-get install z3 # Optional solver The following is optional but is recommended for nicely rendered command line help when running Verilator: -.. code-block:: shell +.. code-block:: bash sudo apt-get install perl-doc To build or run Verilator, the following are optional but should be installed for good performance: -.. code-block:: shell +.. code-block:: bash sudo apt-get install ccache # If present at build, needed for run sudo apt-get install mold # If present at build, needed for run @@ -149,13 +149,13 @@ for good performance: To build Verilator you will need to install these packages; these do not need to be present to run Verilator: -.. code-block:: shell +.. code-block:: bash sudo apt-get install git autoconf flex bison Those developing Verilator itself also need these (see internals.rst): -.. code-block:: shell +.. code-block:: bash sudo apt-get install clang clang-format-18 cmake gdb gprof graphviz lcov sudo apt-get install python3-clang python3-distro yapf3 bear jq @@ -185,7 +185,7 @@ To make use of Verilator FST tracing you will want `GTKwave `__ installed, however this is not required at Verilator build time. -.. code-block:: shell +.. code-block:: bash sudo apt-get install gtkwave # Optional Waveform viewer @@ -209,14 +209,14 @@ Obtain Sources Get the sources from the git repository: (You need to do this only once, ever.) -.. code-block:: shell +.. code-block:: bash git clone https://github.com/verilator/verilator # Only first time ## Note the URL above is not a page you can see with a browser; it's for git only Enter the checkout and determine what version/branch to use: -.. code-block:: shell +.. code-block:: bash cd verilator git pull # Make sure we're up-to-date @@ -231,7 +231,7 @@ Auto Configure Create the configuration script: -.. code-block:: shell +.. code-block:: bash autoconf # Create ./configure script @@ -257,7 +257,7 @@ directory (don't run ``make install``). This allows the easiest experimentation and upgrading, and allows many versions of Verilator to co-exist on a system. -.. code-block:: shell +.. code-block:: bash export VERILATOR_ROOT=`pwd` # if your shell is bash setenv VERILATOR_ROOT `pwd` # if your shell is csh @@ -279,7 +279,7 @@ that may support multiple versions of every tool. Tell configure the eventual destination directory name. We recommend that the destination location include the Verilator version name: -.. code-block:: shell +.. code-block:: bash unset VERILATOR_ROOT # if your shell is bash unsetenv VERILATOR_ROOT # if your shell is csh @@ -291,7 +291,7 @@ the ``bin`` directory to your ``PATH``. Or, if you use `modulecmd `__, you'll want a module file like the following: -.. code-block:: shell +.. code-block:: bash set install_root /CAD_DISK/verilator/{version-number-used-above} unsetenv VERILATOR_ROOT @@ -306,7 +306,7 @@ following: The final option is to eventually install Verilator globally, using configure's default system paths: -.. code-block:: shell +.. code-block:: bash unset VERILATOR_ROOT # if your shell is bash unsetenv VERILATOR_ROOT # if your shell is csh @@ -323,7 +323,7 @@ The command to configure the package was described in the previous step. Developers should configure to have more complete developer tests. Additional packages may be required for these tests. -.. code-block:: shell +.. code-block:: bash export VERILATOR_AUTHOR_SITE=1 # Put in your .bashrc ./configure --enable-longtests ...above options... @@ -334,7 +334,7 @@ Compile Compile Verilator: -.. code-block:: shell +.. code-block:: bash make -j `nproc` # Or if error on `nproc`, the number of CPUs in system @@ -344,7 +344,7 @@ Test Check the compilation by running self-tests: -.. code-block:: shell +.. code-block:: bash make test @@ -356,7 +356,7 @@ If you used any install option other than the `1. Run-in-Place from VERILATOR_ROOT <#_1_run_in_place_from_verilator_root>`__ scheme, install the files: -.. code-block:: shell +.. code-block:: bash make install diff --git a/docs/guide/warnings.rst b/docs/guide/warnings.rst index ee50f6894..ca2ed3373 100644 --- a/docs/guide/warnings.rst +++ b/docs/guide/warnings.rst @@ -103,8 +103,8 @@ List Of Warnings .. code-block:: sv always_comb begin - a = b; - b = 1; + a = b; + b = 1; end Ignoring this warning will only suppress the lint check; it will @@ -275,11 +275,11 @@ List Of Warnings .. code-block:: sv always @(posedge clk) - if (~reset_l) - for (i=0; i<`ARRAY_SIZE; i++) - array[i] <= 0; // Non-blocking assignment inside loop - else - array[address] <= data; + if (~reset_l) + for (i=0; i<`ARRAY_SIZE; i++) + array[i] <= 0; // Non-blocking assignment inside loop + else + array[address] <= data; While this is supported in typical synthesizeable code (including the example above), some complicated cases are not supported. Namely: @@ -577,7 +577,7 @@ List Of Warnings :emphasize-lines: 5 module parameterized - #(parameter int MY_PARAM = 0); + #(parameter int MY_PARAM = 0); endmodule module upper; defparam p0.MY_PARAM = 1; //<--- Warning @@ -598,12 +598,12 @@ List Of Warnings :emphasize-lines: 6 module parameterized - #(parameter int MY_PARAM = 0); + #(parameter int MY_PARAM = 0); endmodule module upper parameterized - #(.MY_PARAM(1)) //<--- Repaired - p0(); + #(.MY_PARAM(1)) //<--- Repaired + p0(); endmodule Other tools with similar warnings: Verible's forbid_defparam_rule. @@ -745,7 +745,7 @@ List Of Warnings :emphasize-lines: 2 typedef enum [3:0] { - WRONG_WIDTH = 33'h3 //<--- Warning + WRONG_WIDTH = 33'h3 //<--- Warning } enum_t; To repair, correct the size of the item's value directly, or use a cast, @@ -831,8 +831,8 @@ List Of Warnings :emphasize-lines: 2 generate - if (PARAM == 1) begin //<--- Warning - end + if (PARAM == 1) begin //<--- Warning + end Results in: @@ -848,8 +848,8 @@ List Of Warnings :emphasize-lines: 2 generate - if (PARAM == 1) begin : gen_param_1 //<--- Repaired - end + if (PARAM == 1) begin : gen_param_1 //<--- Repaired + end Other tools with similar warnings: Verible's generate-label, "All generate block statements must have a label." @@ -885,7 +885,7 @@ List Of Warnings :emphasize-lines: 5 function int function_being_called_as_task; - return 1; + return 1; endfunction initial function_being_called_as_task(); //<--- Warning @@ -904,7 +904,7 @@ List Of Warnings :emphasize-lines: 5 function int function_being_called_as_task; - return 1; + return 1; endfunction initial void'(function_being_called_as_task()); //<--- Repaired @@ -1074,10 +1074,10 @@ List Of Warnings :emphasize-lines: 3 task foo(int local_var); - fork - #10 local_var++; - #20 $display("local_var = %d", local_var); - join_none + fork + #10 local_var++; + #20 $display("local_var = %d", local_var); + join_none endtask In the example above 'local_var' exists only within scope of 'foo', once foo @@ -1099,19 +1099,19 @@ List Of Warnings :emphasize-lines: 4 task foo(int local_var); - fork - #10 begin - int forked_var = local_var; - forked_var++; - end - #20 begin - // Note that we are going to print the original value here, - // as `forked_var`is a local copy that was initialized while - // `foo` was still alive. - int forked_var = local_var; - $display("forked_var = %d", forked_var) - end - join_none + fork + #10 begin + int forked_var = local_var; + forked_var++; + end + #20 begin + // Note that we are going to print the original value here, + // as `forked_var`is a local copy that was initialized while + // `foo` was still alive. + int forked_var = local_var; + $display("forked_var = %d", forked_var) + end + join_none endtask If you need to share its state, another strategy is to ensure it's allocated @@ -1124,10 +1124,10 @@ List Of Warnings int static_var; task foo(); - fork - #10 static_var++; - #20 $display("static_var = %d", static_var); - join_none + fork + #10 static_var++; + #20 $display("static_var = %d", static_var); + join_none endtask However, if you need to be able to instantiate at runtime, the solution would be to @@ -1139,23 +1139,23 @@ List Of Warnings :emphasize-lines: 2 class Wrapper; - int m_var; + int m_var; - // Here we implicitly hold a reference to `this` - task foo(); - fork - #10 m_var++; - #20 $display("this.m_var = %d", m_var); - join_none - endtask + // Here we implicitly hold a reference to `this` + task foo(); + fork + #10 m_var++; + #20 $display("this.m_var = %d", m_var); + join_none + endtask endclass // Here we explicitly hold a handle to an object task bar(Wrapper wrapper); - fork - #10 wrapper.m_var++; - #20 $display("wrapper.m_var = %d", wrapper.m_var); - join_none + fork + #10 wrapper.m_var++; + #20 $display("wrapper.m_var = %d", wrapper.m_var); + join_none endtask .. option:: LITENDIAN @@ -1197,8 +1197,8 @@ List Of Warnings :emphasize-lines: 3 if (something) - statement_in_if; - statement_not_in_if; //<--- Warning + statement_in_if; + statement_not_in_if; //<--- Warning Results in: @@ -1214,7 +1214,7 @@ List Of Warnings :emphasize-lines: 3 if (something) - statement_in_if; + statement_in_if; statement_not_in_if; //<--- Repaired Other tools with similar warnings: GCC -Wmisleading-indentation, @@ -1489,11 +1489,11 @@ List Of Warnings module a; localparam A=1; generate - if (A==0) begin - b b_inst1 (.x(1'b0)); //<--- error nonexistent port - b #(.PX(1'b0)) b_inst2 (); //<--- error nonexistent parameter - end - endgenerate + if (A==0) begin + b b_inst1 (.x(1'b0)); //<--- error nonexistent port + b #(.PX(1'b0)) b_inst2 (); //<--- error nonexistent parameter + end + endgenerate endmodule module b; @@ -1766,9 +1766,9 @@ List Of Warnings wire vec[6:0]; initial begin - index = 7; - ... - if (index < 7) out = vec[index]; // Never will use vec[7] + index = 7; + ... + if (index < 7) out = vec[index]; // Never will use vec[7] Other tools with similar warnings: Icarus Verilog's select-range, "warning: ... [...] is selecting before vector" or "is selecting before @@ -1952,7 +1952,7 @@ List Of Warnings task foo(inout sig); ... endtask // ... always @* begin - foo(bus_we_select_from[2]); // Will get TASKNSVAR error + foo(bus_we_select_from[2]); // Will get TASKNSVAR error end Change this to: @@ -1963,8 +1963,8 @@ List Of Warnings // ... reg foo_temp_out; always @* begin - foo(foo_temp_out); - bus_we_select_from[2] = foo_temp_out; + foo(foo_temp_out); + bus_we_select_from[2] = foo_temp_out; end Verilator doesn't do this conversion for you, as some more complicated diff --git a/test_regress/t/t_assert_comp_bad.out b/test_regress/t/t_assert_comp_bad.out index fd91ed9ac..29fd238ca 100644 --- a/test_regress/t/t_assert_comp_bad.out +++ b/test_regress/t/t_assert_comp_bad.out @@ -1,47 +1,47 @@ --Info: t/t_assert_comp_bad.v:13:7: Elaboration system task message (IEEE 1800-2023 20.11) +-Info: t/t_assert_comp_bad.v:13:5: Elaboration system task message (IEEE 1800-2023 20.11) : ... note: In instance 't' - 13 | $info; - | ^~~~~ --Info: t/t_assert_comp_bad.v:14:7: User elaboration-time info + 13 | $info; + | ^~~~~ +-Info: t/t_assert_comp_bad.v:14:5: User elaboration-time info : ... note: In instance 't' - 14 | $info("User elaboration-time info"); - | ^~~~~ --Info: t/t_assert_comp_bad.v:15:7: Percent=% PctPct=%% Ten=10 + 14 | $info("User elaboration-time info"); + | ^~~~~ +-Info: t/t_assert_comp_bad.v:15:5: Percent=% PctPct=%% Ten=10 : ... note: In instance 't' - 15 | $info("Percent=%% PctPct=%s Ten=%0d", PCTPCT, TEN); - | ^~~~~ -%Warning-USERWARN: t/t_assert_comp_bad.v:16:7: Elaboration system task message (IEEE 1800-2023 20.11) + 15 | $info("Percent=%% PctPct=%s Ten=%0d", PCTPCT, TEN); + | ^~~~~ +%Warning-USERWARN: t/t_assert_comp_bad.v:16:5: Elaboration system task message (IEEE 1800-2023 20.11) : ... note: In instance 't' - 16 | $warning; - | ^~~~~~~~ + 16 | $warning; + | ^~~~~~~~ ... For warning description see https://verilator.org/warn/USERWARN?v=latest ... Use "/* verilator lint_off USERWARN */" and lint_on around source to disable this message. -%Warning-USERWARN: t/t_assert_comp_bad.v:17:7: User elaboration-time warning +%Warning-USERWARN: t/t_assert_comp_bad.v:17:5: User elaboration-time warning : ... note: In instance 't' - 17 | $warning("User elaboration-time warning"); - | ^~~~~~~~ -%Warning-USERWARN: t/t_assert_comp_bad.v:18:7: 1 + 17 | $warning("User elaboration-time warning"); + | ^~~~~~~~ +%Warning-USERWARN: t/t_assert_comp_bad.v:18:5: 1 : ... note: In instance 't' - 18 | $warning(1); - | ^~~~~~~~ -%Warning-USERERROR: t/t_assert_comp_bad.v:19:7: Elaboration system task message (IEEE 1800-2023 20.11) + 18 | $warning(1); + | ^~~~~~~~ +%Warning-USERERROR: t/t_assert_comp_bad.v:19:5: Elaboration system task message (IEEE 1800-2023 20.11) : ... note: In instance 't' - 19 | $error; - | ^~~~~~ + 19 | $error; + | ^~~~~~ ... For warning description see https://verilator.org/warn/USERERROR?v=latest ... Use "/* verilator lint_off USERERROR */" and lint_on around source to disable this message. -%Warning-USERERROR: t/t_assert_comp_bad.v:20:7: User elaboration-time error +%Warning-USERERROR: t/t_assert_comp_bad.v:20:5: User elaboration-time error : ... note: In instance 't' - 20 | $error("User elaboration-time error"); - | ^~~~~~ -%Warning-USERFATAL: t/t_assert_comp_bad.v:21:7: User elaboration-time fatal + 20 | $error("User elaboration-time error"); + | ^~~~~~ +%Warning-USERFATAL: t/t_assert_comp_bad.v:21:5: User elaboration-time fatal : ... note: In instance 't' - 21 | $fatal(0, "User elaboration-time fatal"); - | ^~~~~~ + 21 | $fatal(0, "User elaboration-time fatal"); + | ^~~~~~ ... For warning description see https://verilator.org/warn/USERFATAL?v=latest ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. -%Warning-USERFATAL: t/t_assert_comp_bad.v:22:7: Elaboration system task message (IEEE 1800-2023 20.11) +%Warning-USERFATAL: t/t_assert_comp_bad.v:22:5: Elaboration system task message (IEEE 1800-2023 20.11) : ... note: In instance 't' - 22 | $fatal; - | ^~~~~~ + 22 | $fatal; + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_assert_comp_bad.v b/test_regress/t/t_assert_comp_bad.v index d96d99d2e..03a26d0cd 100644 --- a/test_regress/t/t_assert_comp_bad.v +++ b/test_regress/t/t_assert_comp_bad.v @@ -4,22 +4,22 @@ // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/); +module t; - localparam TEN = 10; - localparam string PCTPCT = "%%"; + localparam TEN = 10; + localparam string PCTPCT = "%%"; - if (1) begin - $info; - $info("User elaboration-time info"); - $info("Percent=%% PctPct=%s Ten=%0d", PCTPCT, TEN); - $warning; - $warning("User elaboration-time warning"); - $warning(1); // Check can convert arguments to format - $error; - $error("User elaboration-time error"); - $fatal(0, "User elaboration-time fatal"); - $fatal; - end + if (1) begin + $info; + $info("User elaboration-time info"); + $info("Percent=%% PctPct=%s Ten=%0d", PCTPCT, TEN); + $warning; + $warning("User elaboration-time warning"); + $warning(1); // Check can convert arguments to format + $error; + $error("User elaboration-time error"); + $fatal(0, "User elaboration-time fatal"); + $fatal; + end endmodule diff --git a/test_regress/t/t_lint_badvltpragma_bad.out b/test_regress/t/t_lint_badvltpragma_bad.out index 8532c03c7..b99627491 100644 --- a/test_regress/t/t_lint_badvltpragma_bad.out +++ b/test_regress/t/t_lint_badvltpragma_bad.out @@ -1,5 +1,5 @@ -%Error-BADVLTPRAGMA: t/t_lint_badvltpragma_bad.v:7:4: Unknown verilator comment: '/*verilator lintt_off WIDTH <--- Warning (lint_off misspelled)*/' - 7 | /*verilator lintt_off WIDTH <--- Warning (lint_off misspelled)*/ - | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error-BADVLTPRAGMA: t/t_lint_badvltpragma_bad.v:7:3: Unknown verilator comment: '/*verilator lintt_off WIDTH <--- Warning (lint_off misspelled)*/' + 7 | /*verilator lintt_off WIDTH <--- Warning (lint_off misspelled)*/ + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/BADVLTPRAGMA?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_lint_badvltpragma_bad.v b/test_regress/t/t_lint_badvltpragma_bad.v index 66dd1e9f8..11181c92c 100644 --- a/test_regress/t/t_lint_badvltpragma_bad.v +++ b/test_regress/t/t_lint_badvltpragma_bad.v @@ -4,6 +4,6 @@ // SPDX-License-Identifier: CC0-1.0 module t; - // verilator lintt_off WIDTH //<--- Warning (lint_off misspelled) - bit one = 2; + // verilator lintt_off WIDTH //<--- Warning (lint_off misspelled) + bit one = 2; endmodule diff --git a/test_regress/t/t_lint_didnotconverge_bad.v b/test_regress/t/t_lint_didnotconverge_bad.v index 544db7390..3c3d87801 100644 --- a/test_regress/t/t_lint_didnotconverge_bad.v +++ b/test_regress/t/t_lint_didnotconverge_bad.v @@ -4,16 +4,16 @@ // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - a, b - ); +module t ( /*AUTOARG*/ + // Outputs + a, b + ); - // verilator lint_off UNOPTFLAT + // verilator lint_off UNOPTFLAT - output logic a, b; + output logic a, b; - always_comb b = ~a; - always_comb a = b; + always_comb b = ~a; + always_comb a = b; endmodule diff --git a/test_regress/t/t_lint_multidriven_bad.out b/test_regress/t/t_lint_multidriven_bad.out index 5c68a4018..a56e0da80 100644 --- a/test_regress/t/t_lint_multidriven_bad.out +++ b/test_regress/t/t_lint_multidriven_bad.out @@ -1,17 +1,17 @@ -%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:21:22: Signal has multiple driving blocks with different clocking: 't.mem' - t/t_lint_multidriven_bad.v:24:7: ... Location of first driving block - 24 | mem[a0] <= d0; - | ^~~ - t/t_lint_multidriven_bad.v:27:7: ... Location of other driving block - 27 | mem[a0] <= d1; - | ^~~ +%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:21:13: Signal has multiple driving blocks with different clocking: 't.mem' + t/t_lint_multidriven_bad.v:24:5: ... Location of first driving block + 24 | mem[a0] <= d0; + | ^~~ + t/t_lint_multidriven_bad.v:27:5: ... Location of other driving block + 27 | mem[a0] <= d1; + | ^~~ ... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest ... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message. -%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:19:22: Signal has multiple driving blocks with different clocking: 'out2' - t/t_lint_multidriven_bad.v:32:7: ... Location of first driving block - 32 | out2[7:0] <= d0; - | ^~~~ - t/t_lint_multidriven_bad.v:35:7: ... Location of other driving block - 35 | out2[15:8] <= d0; - | ^~~~ +%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:19:21: Signal has multiple driving blocks with different clocking: 'out2' + t/t_lint_multidriven_bad.v:32:5: ... Location of first driving block + 32 | out2[7:0] <= d0; + | ^~~~ + t/t_lint_multidriven_bad.v:35:5: ... Location of other driving block + 35 | out2[15:8] <= d0; + | ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_multidriven_bad.v b/test_regress/t/t_lint_multidriven_bad.v index d9f68bdf1..0b3ff7bff 100644 --- a/test_regress/t/t_lint_multidriven_bad.v +++ b/test_regress/t/t_lint_multidriven_bad.v @@ -4,35 +4,35 @@ // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - out, out2, - // Inputs - clk, a0, d0, d1 - ); +module t ( /*AUTOARG*/ + // Outputs + out, out2, + // Inputs + clk, a0, d0, d1 + ); - input clk; - input [1:0] a0; - input [7:0] d0; - input [7:0] d1; - output reg [31:0] out; - output reg [15:0] out2; + input clk; + input [1:0] a0; + input [7:0] d0; + input [7:0] d1; + output reg [31:0] out; + output reg [15:0] out2; - reg [7:0] mem [4]; + reg [7:0] mem[4]; - always @(posedge clk) begin - mem[a0] <= d0; // <--- Warning - end - always @(negedge clk) begin - mem[a0] <= d1; // <--- Warning - end - assign out = {mem[3],mem[2],mem[1],mem[0]}; + always @(posedge clk) begin + mem[a0] <= d0; // <--- Warning + end + always @(negedge clk) begin + mem[a0] <= d1; // <--- Warning + end + assign out = {mem[3], mem[2], mem[1], mem[0]}; - always @(posedge clk) begin - out2[7:0] <= d0; // <--- Warning - end - always @(negedge clk) begin - out2[15:8] <= d0; // <--- Warning - end + always @(posedge clk) begin + out2[7:0] <= d0; // <--- Warning + end + always @(negedge clk) begin + out2[15:8] <= d0; // <--- Warning + end endmodule diff --git a/test_regress/t/t_lint_procassinit_bad.out b/test_regress/t/t_lint_procassinit_bad.out index f54e793a1..ea76c0574 100644 --- a/test_regress/t/t_lint_procassinit_bad.out +++ b/test_regress/t/t_lint_procassinit_bad.out @@ -1,21 +1,21 @@ -%Warning-PROCASSINIT: t/t_lint_procassinit_bad.v:26:21: Procedural assignment to declaration with initial value: 'flop_out' +%Warning-PROCASSINIT: t/t_lint_procassinit_bad.v:26:20: Procedural assignment to declaration with initial value: 'flop_out' : ... note: In instance 't' : ... Location of variable initialization - 26 | logic flop_out = 1; - | ^ - t/t_lint_procassinit_bad.v:30:10: ... Location of variable process write - : ... Perhaps should initialize instead using a reset in this process - 30 | flop_out <= ~in; - | ^~~~~~~~ + 26 | logic flop_out = 1; + | ^ + t/t_lint_procassinit_bad.v:30:7: ... Location of variable process write + : ... Perhaps should initialize instead using a reset in this process + 30 | flop_out <= ~in; + | ^~~~~~~~ ... For warning description see https://verilator.org/warn/PROCASSINIT?v=latest ... Use "/* verilator lint_off PROCASSINIT */" and lint_on around source to disable this message. -%Warning-PROCASSINIT: t/t_lint_procassinit_bad.v:48:21: Procedural assignment to declaration with initial value: 'bad_comb' +%Warning-PROCASSINIT: t/t_lint_procassinit_bad.v:48:20: Procedural assignment to declaration with initial value: 'bad_comb' : ... note: In instance 't' : ... Location of variable initialization - 48 | logic bad_comb = 1; - | ^ - t/t_lint_procassinit_bad.v:51:7: ... Location of variable process write + 48 | logic bad_comb = 1; + | ^ + t/t_lint_procassinit_bad.v:51:5: ... Location of variable process write : ... Perhaps should initialize instead using a reset in this process - 51 | bad_comb = ok2; - | ^~~~~~~~ + 51 | bad_comb = ok2; + | ^~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_procassinit_bad.v b/test_regress/t/t_lint_procassinit_bad.v index 6b8e11d85..c358fcf0b 100644 --- a/test_regress/t/t_lint_procassinit_bad.v +++ b/test_regress/t/t_lint_procassinit_bad.v @@ -4,53 +4,53 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk, reset_l, in, enable - ); - input clk; - input reset_l; - input in; - input enable; +module t ( /*AUTOARG*/ + // Inputs + clk, reset_l, in, enable + ); + input clk; + input reset_l; + input in; + input enable; - logic ok1 = 1; - logic ok2 = 1; - logic ok3 = ok2; + logic ok1 = 1; + logic ok2 = 1; + logic ok3 = ok2; - initial begin - ok1 = 1; - end + initial begin + ok1 = 1; + end - //== Faulty example + //== Faulty example - logic flop_out = 1; // <--- Warning + logic flop_out = 1; // <--- Warning - always @(posedge clk, negedge reset_l) begin - if (enable) begin - flop_out <= ~in; // <--- Use of initialized - end - end + always @(posedge clk, negedge reset_l) begin + if (enable) begin + flop_out <= ~in; // <--- Use of initialized + end + end - //== Fixed example + //== Fixed example - logic flop2_out; + logic flop2_out; - always @(posedge clk, negedge reset_l) begin - if (!reset_l) begin - flop2_out <= '1; // <--- Added reset init - end - else if (enable) begin - flop2_out <= ~in; - end - end + always @(posedge clk, negedge reset_l) begin + if (!reset_l) begin + flop2_out <= '1; // <--- Added reset init + end + else if (enable) begin + flop2_out <= ~in; + end + end - // Combo version - logic bad_comb = 1; // but this is not fine + // Combo version + logic bad_comb = 1; // but this is not fine - always @* begin - bad_comb = ok2; - end + always @* begin + bad_comb = ok2; + end - wire _unused_ok = &{1'b0, flop_out, flop2_out, bad_comb, ok1, ok2, ok3}; + wire _unused_ok = &{1'b0, flop_out, flop2_out, bad_comb, ok1, ok2, ok3}; endmodule diff --git a/test_regress/t/t_lint_stmtdly_bad.out b/test_regress/t/t_lint_stmtdly_bad.out index a028e83e0..5785b9063 100644 --- a/test_regress/t/t_lint_stmtdly_bad.out +++ b/test_regress/t/t_lint_stmtdly_bad.out @@ -1,7 +1,7 @@ -%Warning-STMTDLY: t/t_lint_stmtdly_bad.v:10:7: Ignoring delay on this statement due to --no-timing +%Warning-STMTDLY: t/t_lint_stmtdly_bad.v:10:5: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' - 10 | #100 $finish; - | ^ + 10 | #100 $finish; + | ^ ... For warning description see https://verilator.org/warn/STMTDLY?v=latest ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_stmtdly_bad.v b/test_regress/t/t_lint_stmtdly_bad.v index 3684bbb30..f32ff0dda 100644 --- a/test_regress/t/t_lint_stmtdly_bad.v +++ b/test_regress/t/t_lint_stmtdly_bad.v @@ -4,10 +4,10 @@ // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/); +module t ( /*AUTOARG*/); - initial begin - #100 $finish; //<--- Warning - end + initial begin + #100 $finish; //<--- Warning + end endmodule diff --git a/test_regress/t/t_var_bad_hide_docs.out b/test_regress/t/t_var_bad_hide_docs.out index 78467eb5a..5f7ff29b4 100644 --- a/test_regress/t/t_var_bad_hide_docs.out +++ b/test_regress/t/t_var_bad_hide_docs.out @@ -1,6 +1,6 @@ -%Warning-VARHIDDEN: t/t_var_bad_hide_docs.v:8:12: Declaration of signal hides declaration in upper scope: 't' - 8 | integer t; - | ^ +%Warning-VARHIDDEN: t/t_var_bad_hide_docs.v:8:11: Declaration of signal hides declaration in upper scope: 't' + 8 | integer t; + | ^ t/t_var_bad_hide_docs.v:7:8: ... Location of original declaration 7 | module t; | ^ diff --git a/test_regress/t/t_var_bad_hide_docs.v b/test_regress/t/t_var_bad_hide_docs.v index 964f69f5a..ff91817b3 100644 --- a/test_regress/t/t_var_bad_hide_docs.v +++ b/test_regress/t/t_var_bad_hide_docs.v @@ -5,5 +5,5 @@ // SPDX-License-Identifier: CC0-1.0 module t; - integer t; //<--- Warning ('t' hidden by module 't') + integer t; //<--- Warning ('t' hidden by module 't') endmodule