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Verilog format
This commit is contained in:
Veripool API Bot
committed by
Wilson Snyder
Wilson Snyder
parent
5821d0697c
commit
ce4d35aa85
@@ -4,150 +4,148 @@
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// SPDX-FileCopyrightText: 2009 Iztok Jeras
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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module t (
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input clk
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);
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input clk;
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logic [1:0][3:0][3:0] array_simp; // descending range array
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logic [1:0] [3:0] [3:0] array_simp; // descending range array
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logic [3:0] array_oned;
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logic [3:0] array_oned;
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// verilog_format: off
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initial begin
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array_oned = '{2:1'b1, 0:1'b1, default:1'b0};
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if (array_oned != 4'b0101) $stop;
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initial begin
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array_oned = '{2:1'b1, 0:1'b1, default:1'b0};
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if (array_oned != 4'b0101) $stop;
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array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0};
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if (array_simp[0] !== 16'h3210) $stop;
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array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0};
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if (array_simp[0] !== 16'h3210) $stop;
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// verilator lint_off WIDTH
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array_simp[0] = '{ 3 ,2 ,1, 0 };
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// verilator lint_on WIDTH
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if (array_simp[0] !== 16'h3210) $stop;
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// verilator lint_off WIDTH
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array_simp[0] = '{ 3 ,2 ,1, 0 };
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// verilator lint_on WIDTH
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if (array_simp[0] !== 16'h3210) $stop;
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// Doesn't seem to work for unpacked arrays in other simulators
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//if (array_simp[0] !== 16'h3210) $stop;
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//array_simp[0] = '{ 1:4'd3, default:13};
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//if (array_simp[0] !== 16'hDD3D) $stop;
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// Doesn't seem to work for unpacked arrays in other simulators
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//if (array_simp[0] !== 16'h3210) $stop;
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//array_simp[0] = '{ 1:4'd3, default:13};
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//if (array_simp[0] !== 16'hDD3D) $stop;
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array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }};
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if (array_simp !== 32'h3210_1234) $stop;
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array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }};
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if (array_simp !== 32'h3210_1234) $stop;
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// IEEE says '{} allowed only on assignments, not !=, ==.
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// IEEE says '{} allowed only on assignments, not !=, ==.
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// Doesn't seem to work for unpacked arrays in other simulators
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array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }};
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if (array_simp !== 32'h3210_3210) $stop;
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// Doesn't seem to work for unpacked arrays in other simulators
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array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }};
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if (array_simp !== 32'h3210_3210) $stop;
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array_simp = '{2{ '{4{ 4'd3 }} }};
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if (array_simp !== 32'h3333_3333) $stop;
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array_simp = '{2{ '{4{ 4'd3 }} }};
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if (array_simp !== 32'h3333_3333) $stop;
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// Not legal in other simulators - replication doesn't match
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// However IEEE suggests this is legal.
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//array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2}
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// Not legal in other simulators - replication doesn't match
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// However IEEE suggests this is legal.
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//array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2}
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$write("*-* All Finished *-*\n");
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$finish;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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//====================
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//====================
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// parameters for array sizes
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localparam WA = 4; // address dimension size
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localparam WB = 4; // bit dimension size
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// parameters for array sizes
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localparam WA = 4; // address dimension size
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localparam WB = 4; // bit dimension size
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localparam NO = 11; // number of access events
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localparam NO = 11; // number of access events
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// 2D packed arrays
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logic [WA-1:0] [WB-1:0] array_dsc; // descending range array
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/* verilator lint_off ASCRANGE */
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logic [0:WA-1] [0:WB-1] array_asc; // ascending range array
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/* verilator lint_on ASCRANGE */
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// 2D packed arrays
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logic [WA-1:0] [WB-1:0] array_dsc; // descending range array
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/* verilator lint_off ASCRANGE */
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logic [0:WA-1] [0:WB-1] array_asc; // ascending range array
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/* verilator lint_on ASCRANGE */
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integer cnt = 0;
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integer cnt = 0;
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// event counter
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always @ (posedge clk) begin
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cnt <= cnt + 1;
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end
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// event counter
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always @ (posedge clk) begin
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cnt <= cnt + 1;
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end
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// finish report
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always @ (posedge clk)
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if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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// finish report
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always @ (posedge clk)
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if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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// descending range
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always @ (posedge clk)
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if (cnt[1:0]==2'd0) begin
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// initialize to defaults (all bits 1'b0)
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if (cnt[30:2]== 0) array_dsc <= '0;
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else if (cnt[30:2]== 1) array_dsc <= '0;
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else if (cnt[30:2]== 2) array_dsc <= '0;
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else if (cnt[30:2]== 3) array_dsc <= '0;
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else if (cnt[30:2]== 4) array_dsc <= '0;
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else if (cnt[30:2]== 5) array_dsc <= '0;
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else if (cnt[30:2]== 6) array_dsc <= '0;
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else if (cnt[30:2]== 7) array_dsc <= '0;
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else if (cnt[30:2]== 8) array_dsc <= '0;
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else if (cnt[30:2]== 9) array_dsc <= '0;
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else if (cnt[30:2]==10) array_dsc <= '0;
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end else if (cnt[1:0]==2'd1) begin
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// write data into whole or part of the array using literals
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if (cnt[30:2]== 0) begin end
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else if (cnt[30:2]== 1) array_dsc <= '{ 3 ,2 ,1, 0 };
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else if (cnt[30:2]== 2) array_dsc <= '{default:13};
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else if (cnt[30:2]== 3) array_dsc <= '{0:4, 1:5, 2:6, 3:7};
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else if (cnt[30:2]== 4) array_dsc <= '{2:15, default:13};
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else if (cnt[30:2]== 5) array_dsc <= '{WA { {WB/2 {2'b10}} }};
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else if (cnt[30:2]== 6) array_dsc <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3};
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end else if (cnt[1:0]==2'd2) begin
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// chack array agains expected value
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if (cnt[30:2]== 0) begin if (array_dsc !== 16'b0000000000000000) begin $display("%b", array_dsc); $stop(); end end
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else if (cnt[30:2]== 1) begin if (array_dsc !== 16'b0011001000010000) begin $display("%b", array_dsc); $stop(); end end
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else if (cnt[30:2]== 2) begin if (array_dsc !== 16'b1101110111011101) begin $display("%b", array_dsc); $stop(); end end
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else if (cnt[30:2]== 3) begin if (array_dsc !== 16'b0111011001010100) begin $display("%b", array_dsc); $stop(); end end
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else if (cnt[30:2]== 4) begin if (array_dsc !== 16'b1101111111011101) begin $display("%b", array_dsc); $stop(); end end
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else if (cnt[30:2]== 5) begin if (array_dsc !== 16'b1010101010101010) begin $display("%b", array_dsc); $stop(); end end
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else if (cnt[30:2]== 6) begin if (array_dsc !== 16'b1001101010111100) begin $display("%b", array_dsc); $stop(); end end
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end
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// descending range
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always @ (posedge clk)
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if (cnt[1:0]==2'd0) begin
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// initialize to defaults (all bits 1'b0)
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if (cnt[30:2]== 0) array_dsc <= '0;
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else if (cnt[30:2]== 1) array_dsc <= '0;
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else if (cnt[30:2]== 2) array_dsc <= '0;
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else if (cnt[30:2]== 3) array_dsc <= '0;
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else if (cnt[30:2]== 4) array_dsc <= '0;
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else if (cnt[30:2]== 5) array_dsc <= '0;
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else if (cnt[30:2]== 6) array_dsc <= '0;
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else if (cnt[30:2]== 7) array_dsc <= '0;
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else if (cnt[30:2]== 8) array_dsc <= '0;
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else if (cnt[30:2]== 9) array_dsc <= '0;
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else if (cnt[30:2]==10) array_dsc <= '0;
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end else if (cnt[1:0]==2'd1) begin
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// write data into whole or part of the array using literals
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if (cnt[30:2]== 0) begin end
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else if (cnt[30:2]== 1) array_dsc <= '{ 3 ,2 ,1, 0 };
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else if (cnt[30:2]== 2) array_dsc <= '{default:13};
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else if (cnt[30:2]== 3) array_dsc <= '{0:4, 1:5, 2:6, 3:7};
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else if (cnt[30:2]== 4) array_dsc <= '{2:15, default:13};
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else if (cnt[30:2]== 5) array_dsc <= '{WA { {WB/2 {2'b10}} }};
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else if (cnt[30:2]== 6) array_dsc <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3};
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end else if (cnt[1:0]==2'd2) begin
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// chack array agains expected value
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if (cnt[30:2]== 0) begin if (array_dsc !== 16'b0000000000000000) begin $display("%b", array_dsc); $stop(); end end
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else if (cnt[30:2]== 1) begin if (array_dsc !== 16'b0011001000010000) begin $display("%b", array_dsc); $stop(); end end
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else if (cnt[30:2]== 2) begin if (array_dsc !== 16'b1101110111011101) begin $display("%b", array_dsc); $stop(); end end
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else if (cnt[30:2]== 3) begin if (array_dsc !== 16'b0111011001010100) begin $display("%b", array_dsc); $stop(); end end
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else if (cnt[30:2]== 4) begin if (array_dsc !== 16'b1101111111011101) begin $display("%b", array_dsc); $stop(); end end
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else if (cnt[30:2]== 5) begin if (array_dsc !== 16'b1010101010101010) begin $display("%b", array_dsc); $stop(); end end
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else if (cnt[30:2]== 6) begin if (array_dsc !== 16'b1001101010111100) begin $display("%b", array_dsc); $stop(); end end
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end
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// ascending range
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always @ (posedge clk)
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if (cnt[1:0]==2'd0) begin
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// initialize to defaults (all bits 1'b0)
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if (cnt[30:2]== 0) array_asc <= '0;
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else if (cnt[30:2]== 1) array_asc <= '0;
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else if (cnt[30:2]== 2) array_asc <= '0;
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else if (cnt[30:2]== 3) array_asc <= '0;
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else if (cnt[30:2]== 4) array_asc <= '0;
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else if (cnt[30:2]== 5) array_asc <= '0;
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else if (cnt[30:2]== 6) array_asc <= '0;
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else if (cnt[30:2]== 7) array_asc <= '0;
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else if (cnt[30:2]== 8) array_asc <= '0;
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else if (cnt[30:2]== 9) array_asc <= '0;
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else if (cnt[30:2]==10) array_asc <= '0;
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end else if (cnt[1:0]==2'd1) begin
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// write data into whole or part of the array using literals
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if (cnt[30:2]== 0) begin end
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else if (cnt[30:2]== 1) array_asc <= '{ 3 ,2 ,1, 0 };
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else if (cnt[30:2]== 2) array_asc <= '{default:13};
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else if (cnt[30:2]== 3) array_asc <= '{3:4, 2:5, 1:6, 0:7};
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else if (cnt[30:2]== 4) array_asc <= '{1:15, default:13};
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else if (cnt[30:2]== 5) array_asc <= '{WA { {WB/2 {2'b10}} }};
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else if (cnt[30:2]==10) array_asc <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3};
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end else if (cnt[1:0]==2'd2) begin
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// chack array agains expected value
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if (cnt[30:2]== 0) begin if (array_asc !== 16'b0000000000000000) begin $display("%b", array_asc); $stop(); end end
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else if (cnt[30:2]== 1) begin if (array_asc !== 16'b0011001000010000) begin $display("%b", array_asc); $stop(); end end
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else if (cnt[30:2]== 2) begin if (array_asc !== 16'b1101110111011101) begin $display("%b", array_asc); $stop(); end end
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else if (cnt[30:2]== 3) begin if (array_asc !== 16'b0111011001010100) begin $display("%b", array_asc); $stop(); end end
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else if (cnt[30:2]== 4) begin if (array_asc !== 16'b1101111111011101) begin $display("%b", array_asc); $stop(); end end
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else if (cnt[30:2]== 5) begin if (array_asc !== 16'b1010101010101010) begin $display("%b", array_asc); $stop(); end end
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else if (cnt[30:2]==10) begin if (array_asc !== 16'b1001101010111100) begin $display("%b", array_asc); $stop(); end end
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end
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// ascending range
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always @ (posedge clk)
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if (cnt[1:0]==2'd0) begin
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// initialize to defaults (all bits 1'b0)
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if (cnt[30:2]== 0) array_asc <= '0;
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else if (cnt[30:2]== 1) array_asc <= '0;
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else if (cnt[30:2]== 2) array_asc <= '0;
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else if (cnt[30:2]== 3) array_asc <= '0;
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else if (cnt[30:2]== 4) array_asc <= '0;
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else if (cnt[30:2]== 5) array_asc <= '0;
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else if (cnt[30:2]== 6) array_asc <= '0;
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else if (cnt[30:2]== 7) array_asc <= '0;
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else if (cnt[30:2]== 8) array_asc <= '0;
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else if (cnt[30:2]== 9) array_asc <= '0;
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else if (cnt[30:2]==10) array_asc <= '0;
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end else if (cnt[1:0]==2'd1) begin
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// write data into whole or part of the array using literals
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if (cnt[30:2]== 0) begin end
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else if (cnt[30:2]== 1) array_asc <= '{ 3 ,2 ,1, 0 };
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else if (cnt[30:2]== 2) array_asc <= '{default:13};
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else if (cnt[30:2]== 3) array_asc <= '{3:4, 2:5, 1:6, 0:7};
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else if (cnt[30:2]== 4) array_asc <= '{1:15, default:13};
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else if (cnt[30:2]== 5) array_asc <= '{WA { {WB/2 {2'b10}} }};
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else if (cnt[30:2]==10) array_asc <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3};
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end else if (cnt[1:0]==2'd2) begin
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// chack array agains expected value
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if (cnt[30:2]== 0) begin if (array_asc !== 16'b0000000000000000) begin $display("%b", array_asc); $stop(); end end
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else if (cnt[30:2]== 1) begin if (array_asc !== 16'b0011001000010000) begin $display("%b", array_asc); $stop(); end end
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else if (cnt[30:2]== 2) begin if (array_asc !== 16'b1101110111011101) begin $display("%b", array_asc); $stop(); end end
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else if (cnt[30:2]== 3) begin if (array_asc !== 16'b0111011001010100) begin $display("%b", array_asc); $stop(); end end
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else if (cnt[30:2]== 4) begin if (array_asc !== 16'b1101111111011101) begin $display("%b", array_asc); $stop(); end end
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else if (cnt[30:2]== 5) begin if (array_asc !== 16'b1010101010101010) begin $display("%b", array_asc); $stop(); end end
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else if (cnt[30:2]==10) begin if (array_asc !== 16'b1001101010111100) begin $display("%b", array_asc); $stop(); end end
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end
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endmodule
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